ADE7518ASTZF16-RL Analog Devices Inc, ADE7518ASTZF16-RL Datasheet - Page 15

• Manufacturer Part Number: ADE7518ASTZF16-RL
• Description: 1-Phase Energy Meter IC
• Manufacturer: Analog Devices Inc

Specifications of ADE7518ASTZF16-RL

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (16 kB)
• Controller Series: ADE75xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 12. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
35 to 20
36
Mnemonic
COM3/FP27
COM2/FP28
COM1
COM0
P1.2/FP25
P1.3/T2EX/FP24
P1.4/T2/FP23
P1.5/FP22
P1.6/FP21
P1.7/FP20
P0.1/FP19
P2.0/FP18
P2.1/FP17
P2.2/FP16
LCDVC
LCDVP2
LCDVB
LCDVA
LCDVP1
FP0 to F15
P1.1/TxD
P1.3/T2EX/FP24
Common Output 3 or LCD Segment Output 27. COM3 is used for LCD backplane.
Common Output 2 or LCD Segment Output 28. COM2 is used for LCD backplane.
Common Output 1. COM1 is used for LCD backplane.
Common Output 0. COM0 is used for LCD backplane.
General-Purpose Digital I/O Port 1.3, Timer 2 Control Input, or LCD Segment Output 24.
General-Purpose Digital I/O Port 1.4, Timer 2 Input, or LCD Segment Output 23.
General-Purpose Digital I/O Port 1.7 or LCD Segment Output 20.
General-Purpose Digital I/O Port 0.1 or LCD Segment Output 19.
General-Purpose Digital I/O Port 2.0 or LCD Segment Output 18.
General-Purpose Digital I/O Port 2.1 or LCD Segment Output 17.
General-Purpose Digital I/O Port 2.2 or LCD Segment Output 16.
This pin is internally connected to LCDVP1 (see the LCD Driver section).
General-Purpose Digital I/O Port 1.1 or Transmitter Data Output (Asynchronous).
Description
General-Purpose Digital I/O Port 1.2 or LCD Segment Output 25.
General-Purpose Digital I/O Port 1.5 or LCD Segment Output 22.
General-Purpose Digital I/O Port 1.6 or LCD Segment Output 21.
This pin is internally connected to V
generate the top two voltages for the LCD waveforms (see the LCD Driver section).
This pin is an input voltage for the LCD driver. A resistor should be connected between LCDVB and LCDVC to
generate an intermediate voltage for the LCD driver. In 1/3 bias LCD mode, another resistor must be
connected between LCDVB and LCDVA to generate another intermediate voltage. In 1/2 bias LCD mode,
LCDVB and LCDVA are internally connected (see the LCD Driver section).
This pin is an input voltage for the LCD driver. A resistor should be connected between LCDVA and LCDVP1
to generate an intermediate voltage for the LCD driver. In 1/3 bias LCD mode, another resistor must be
connected between LCDVB and LCDVA to generate another intermediate voltage. In 1/2 bias LCD mode,
LCDVB and LCDVA are internally connected (see the LCD Driver section).
This pin is an input voltage for the LCD driver. A resistor should be connected between LCDVA and LCDVP1
to generate an intermediate voltage for the LCD driver. Another resistor must be connected between
LCDVP1 and DGND to generate another intermediate voltage (see the LCD Driver section).
LCD Segment Output 0 to LCD Segment Output 15.
P1.4/T2/FP23
COM3/FP27
COM2/FP28
P1.2/FP25
P1.5/FP22
P1.6/FP21
P1.7/FP20
P0.1/FP19
P2.0/FP18
P2.1/FP17
P2.2/FP16
LCDVP2
LCDVC
COM1
COM0
10
12
13
14
15
16
11
1
4
2
3
5
6
7
8
9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PIN 1
Figure 8. Pin Configuration
Rev. 0 | Page 15 of 128
(Not to Scale)
ADE7518
TOP VIEW
DD
. A resistor should be connected between LCDVC and LCDVB to
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
INT0
XTAL1
XTAL2
BCTRL/INT1/P0.0
SDEN/P2.3
P0.2/CF1/RTCCAL
P0.3/CF2
P0.4/MOSI/SDATA
P0.5/MISO
P0.6/SCLK/T0
P0.7/SS/T1
P1.0/RxD
P1.1/TxD
FP0
FP1
FP2
ADE7518