ADE7518ASTZF16-RL Analog Devices Inc, ADE7518ASTZF16-RL Datasheet - Page 82

• Manufacturer Part Number: ADE7518ASTZF16-RL
• Description: 1-Phase Energy Meter IC
• Manufacturer: Analog Devices Inc

Specifications of ADE7518ASTZF16-RL

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (16 kB)
• Controller Series: ADE75xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADE7518
Table 69. LCD Configuration X SFR (LCDCONX, 0x9C)
Bit
7
6
5 to 0
Table 70. LCD Configuration Y SFR (LCDCONY, 0xB1)
Bit
7
6
5 to 2
1
0
Table 71. LCD Clock SFR (LCDCLK, 0x96)
Bit
7 to 6
5 to 4
3 to 0
Mnemonic
Reserved
EXTRES
Reserved
Mnemonic
Reserved
INV_LVL
Reserved
UPDATEOVER
REFRESH
Mnemonic
BLKMOD[1:0]
BLKFREQ[1:0]
FD[3:0]
Default
0
0
0
Default
0
0
0
0
0
Default
00
00
0
Description
Reserved.
External Resistor Ladder Selection Bit.
EXTRES
0
1
These bits should be set to 0 for proper operation.
Description
This bit should be kept cleared for proper operation.
Frame Inversion Mode Enable Bit. If this bit is set, frames are inverted every other frame. If this bit is
cleared, frames are not inverted.
These bits should be kept cleared for proper operation.
Update Finished Flag Bit. This bit is updated by the LCD driver. When set, this bit indicates that the
LCD memory has been updated and a new frame has begun.
Refresh LCD Data Memory Bit. This bit should be set by the user. When this bit is set, the LCD driver
does not use the data in the LCD data registers to update the display. The LCD data registers can be
updated by the 8052. When this bit is cleared, the LCD driver uses the data in the LCD data registers to
update the display at the next frame.
Blink Mode Clock Source Configuration Bits.
BLKMOD[1:0]
00
01
10
11
Blink Rate Configuration Bits. These bits control the LCD blink rate if BLKMOD[1:0] = 11.
BLKFREQ[1:0]
00
01
10
11
LCD Frame Rate Selection Bits. See Table 72 and Table 73.
Description
Result
External resistor ladder is disabled.
External resistor ladder is enabled.
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Result
The blink rate is controlled by software. The display is off.
The blink rate is controlled by software. The display is on.
The blink rate is 2 Hz.
The blink rate is set by BLKFREQ[1:0].
Result (Blink Rate)
1 Hz
1/2 Hz
1/3 Hz
1/4 Hz