ADE7518ASTZF16-RL Analog Devices Inc, ADE7518ASTZF16-RL Datasheet - Page 64

1-Phase Energy Meter IC

ADE7518ASTZF16-RL

Manufacturer Part Number
ADE7518ASTZF16-RL
Description
1-Phase Energy Meter IC
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADE7518ASTZF16-RL

Applications
Energy Measurement
Core Processor
8052
Program Memory Type
FLASH (16 kB)
Controller Series
ADE75xx
Ram Size
512 x 8
Interface
I²C, SPI, UART
Number Of I /o
20
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADE7518ASTZF16-RL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
ADE7518
Table 47. Program Control SFR (PCON, 0x87)
Bit
7
6 to 0
Table 48. Data Pointer Low SFR (DPL, 0x82)
Bit
7 to 0
Table 49. Data Pointer High SFR (DPH, 0x83)
Bit
7 to 0
Table 52. Configuration SFR (CFG, 0xAF)
Bit
7
6
5
4
3 to 2
1 to 0
Default
0
Default
0
Mnemonic
Reserved
EXTEN
SCPS
MOD38EN
Reserved
XREN1,
XREN0
Default
0
0
Description
Contain the high byte of the data pointer.
Description
Contain the low byte of the data pointer.
Description
SMOD Bit. Double baud rate control.
Reserved. Should be left cleared.
This bit should be left set for proper operation.
Enhanced UART Enable Bit.
Synchronous Communication Selection Bit.
38 kHz Modulation Enable Bit.
Description
EXTEN
0
1
SCPS
0
1
MOD38EN
0
1
XRENx
XREN1 OR XREN0 = 1
XREN1 AND XREN0 = 0
Result
Standard 8052 UART without enhanced error-checking features.
Enhanced UART with enhanced error checking (see the UART Additional Features section).
Result
I
SPI port is selected for control of the shared I
Result
38 kHz modulation is disabled.
38 kHz modulation is enabled on the pins selected by the MOD38[7:0] bits in the
Extended Port Configuration SFR (EPCFG, 0x9F).
Result
Enables MOVX instruction to use 256 bytes of extended RAM.
Disables MOVX instruction.
2
C port is selected for control of the shared I
Rev. 0 | Page 64 of 128
Table 50. Data Pointer SFR (DPTR, 0x82 and 0x83)
Bit
15 to 0
Table 51. Stack Pointer SFR (SP, 0x81)
Bit
7 to 0
Default
7
Default
0
2
2
C/SPI pins (MOSI, MISO, SCLK, and SS) and SFRs.
C/SPI pins (MOSI, MISO, SCLK, and SS) and SFRs.
Description
Contain the eight LSBs of the pointer for the
stack.
Description
Contain the 2-byte address of the data pointer.
DPTR is a combination of DPH and DPL SFRs.

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