ADE7518ASTZF16-RL Analog Devices Inc, ADE7518ASTZF16-RL Datasheet - Page 59

• Manufacturer Part Number: ADE7518ASTZF16-RL
• Description: 1-Phase Energy Meter IC
• Manufacturer: Analog Devices Inc

Specifications of ADE7518ASTZF16-RL

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (16 kB)
• Controller Series: ADE75xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPARENT ENERGY CALCULATION
The apparent energy is given as the integer of the apparent power.
The ADE7518 achieves the integration of the apparent power
signal by continuously accumulating the apparent power signal
in an internal 48-bit register. The apparent energy register
(VAHR[23:0]) represents the upper 24 bits of this internal
register. This discrete time accumulation or summation is
equivalent to integration in continuous time. Equation 32
expresses the relationship.
where:
n is the discrete time sample number.
T is the sample period.
The discrete time sample period (T) for the accumulation
register in the ADE7518 is 1.22 μs (5/MCLK).
Figure 63 shows this discrete time integration or accumulation.
The apparent power signal is continuously added to the internal
register. This addition is a signed addition even if the apparent
energy theoretically remains positive.
The 49 bits of the internal register are divided by VADIV. If the
value in the VADIV register is 0, the internal apparent energy
register is divided by 1. VADIV is an 8-bit unsigned register.
The upper 24 bits are then written in the 24-bit apparent energy
register (VAHR[23:0]). The RVAHR register (24 bits long) is
Apparent
Apparent
Energy
Energy
=
=
∫
Apparent
lim
T
→
0
⎧
⎨
⎩
∑
n
∞
=
0
Apparent
Power
APPARENT POWER
) (
t
dt
I
rms
Power
or
T
(
APPARENT
POWER SIGNAL = P
nT
TIME (nT)
Figure 63. Apparent Energy Calculation
)
×
T
+
⎫
⎬
⎭
Rev. 0 | Page 59 of 128
(31)
(32)
+
48
48
23
VADIV
VAHR[23:0]
provided to read the apparent energy. This register is reset to 0
after a read operation.
Note that the apparent energy register is unsigned. By setting
the VAEHF and VAEOF bits in the Interrupt Enable 2 SFR
(MIRQENM, 0xDA), the ADE7518 can be configured to issue
an ADE interrupt to the 8052 core when the apparent energy
register is half-full or when an overflow occurs. The half-full
interrupt for the unsigned apparent energy register is based on
24 bits as opposed to 23 bits for the signed active energy register.
Integration Times Under Steady Load: Apparent Energy
As mentioned in the Apparent Energy Calculation section, the
discrete time sample period (T) for the accumulation register
is 1.22 μs (5/MCLK). With full-scale sinusoidal signals on the
analog inputs and the VAGAIN register set to 0x000, the average
word value from the apparent power stage is 0x1A36E2 (see the
Apparent Power Calculation section). The maximum value that
can be stored in the apparent energy register before it overflows
is 2
register, which can store 248 or 0xFFFF,FFFF,FFFF before it
overflows. Therefore, the integration time under these conditions
with VADIV = 0 is calculated as follows:
When VADIV is set to a value other than 0, the integration time
varies, as shown in Equation 34.
APPARENT POWER OR I
ACCUMULATED (INTEGRATED)
IN THE APPARENT ENERGY
REGISTER
%
24
Time =
Time = Time
or 0xFF,FFFF. The average word value is added to the internal
0xFFFF,
0
0xD055
FFFF,
WDIV = 0
0
FFFF
0
rms
IS
× VADIV
×
. 1
22
μ
s
=
199
sec
=
. 3
33
ADE7518
min
(33)
(34)