ADE7518ASTZF16-RL Analog Devices Inc, ADE7518ASTZF16-RL Datasheet - Page 24

• Manufacturer Part Number: ADE7518ASTZF16-RL
• Description: 1-Phase Energy Meter IC
• Manufacturer: Analog Devices Inc

Specifications of ADE7518ASTZF16-RL

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (16 kB)
• Controller Series: ADE75xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADE7518
Table 21. Scratch Pad 2 SFR (SCRATCH2, 0xFC)
Bit
7 to 0
Table 22. Scratch Pad 3 SFR (SCRATCH3, 0xFD)
Bit
7 to 0
Table 23. Scratch Pad 4 SFR (SCRATCH4, 0xFE)
Bit
7 to 0
Clearing the Scratch Pad Registers (SCRATCH1, 0xFB to SCRATCH4, 0xFE)
Note that these scratch pad registers are only cleared when the part loses V
PLL reset and, therefore, need to be set correctly in these situations.
Table 24. Power Control SFR (POWCON, 0xC5)
Bit
7
6
5
4
3
2 to 0
Writing to the Power Control SFR (POWCON, 0xC5)
Writing data to the POWCON SFR involves writing 0xA7 into the Key SFR (KYREG, 0xC1), which is described in Table 105, followed by
a write to the POWCON SFR. For example,
MOV KYREG,#0A7h
MOV POWCON,#10h
Mnemonic
SCRATCH2
Mnemonic
SCRATCH3
Mnemonic
SCRATCH4
Mnemonic
Reserved
METER_OFF
Reserved
COREOFF
Reserved
CD[2:0]
Default
0
Default
0
Default
0
;Write KYREG to 0xA7 to get write access to the POWCON SFR
;Shutdown the core
Default
1
0
0
0
0
010
Description
Value can be written/read in this register. This value is maintained in all the power saving modes.
Description
Value can be written/read in this register. This value is maintained in all the power saving modes.
Description
Value can be written/read in this register. This value is maintained in all the power saving modes.
Description
Reserved.
Set this bit to turn off the modulators and energy metering DSP circuitry to reduce power if
metering functions are not needed in PSM0.
This bit should be kept at 0 for proper operation.
Set this bit to shut down the core and enter PSM2 if in PSM1 operating mode.
Reserved.
Controls the core clock frequency, f
CD[2:0]
000
001
010
011
100
101
110
111
Rev. 0 | Page 24 of 128
Result (f
4.096
2.048
1.024
0.512
0.256
0.128
0.064
0.032
CORE
DD
in MHz)
and V
CORE
BAT
. They are not cleared by software, watchdog, or
. f
CORE
= 4.096 MHz/2
CD
.