ADN4604ASVZ-RL Analog Devices Inc, ADN4604ASVZ-RL Datasheet - Page 16

• Manufacturer Part Number: ADN4604ASVZ-RL
• Description: 4.25Gbps 16x16 Crossbar Switch
• Manufacturer: Analog Devices Inc
• Series: XStream™r

Specifications of ADN4604ASVZ-RL

• Function: Crosspoint Switch
• Circuit: 1 x 16:16
• On-state Resistance: 56 Ohm
• Voltage Supply Source: Single Supply
• Voltage - Supply, Single/dual (±): 2.7 V ~ 3.6 V
• Current - Supply: 95mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADN4604
THEORY OF OPERATION
INTRODUCTION
The ADN4604 is a 16 × 16, buffered, asynchronous crosspoint
switch that provides input equalization, output preemphasis,
and output level programming capabilities. The receivers
integrate an equalizer that is optimized to compensate for
typical backplane losses. The switch supports multicast and
broadcast operation, allowing the ADN4604 to work in
redundancy and port-replication applications. The part offers
extensively programmable output levels and preemphasis
settings.
The configuration of the crosspoint is controlled through
a serial interface. This interface supports both I
protocols, which can be selected using the I2C /SPI dedicated
control pin. There are two I
described in
Table 6. Serial Interface Control Modes
Pin
No.
50
51
75
76
ADDR1/SDI
ADDR0/CS
SDA/SDO
SCL/SCK
UPDATE
IP[15:0]
IN[15:0]
I2C/SPI
RESET
V
V
TTIE
TTIW
,
Pin
Name
ADDR1
ADDR0
SDA
SCL
Table 6
CONNECTION
CONNECTION
INTERFACE
CONTROL
I2C /SPI = 0
RX
EQ
SERIAL
LOGIC
MAP 0
MAP 1
.
Pin
Function
I
MSB
I
LSB
I
I
2
2
2
2
Figure 39. Block Diagram
C Address
C Address
C Data
C Clock
DV
2
SWITCH
CC
MATRIX
C address pins available as
16 × 16
V
V
CC
EE
HOOKUP
OUTPUT
TABLE
LEVEL
Pin
Name
SDI
CS
SDO
SCK
ADN4604
EMPHASIS
PRE-
TX
I2C /SPI = 1
PER-PORT
SETTINGS
OUTPUT
2
LEVEL
C and SPI
Pin
Function
SPI Data
Input
SPI Chip
Select
SPI Data
Output
SPI Clock
OP[15:0]
V
V
ON[15:0]
TTON
TTOS
Rev. 0 | Page 16 of 40
,
RECEIVERS
Input Structure and Input Levels
The ADN4604 receiver inputs incorporate 50 Ω termination
resistors, ESD protection, and a fixed equalizer that is optimized for
operation over long backplane traces. Each receive channel also
provides a positive/negative (P/N) inversion function, which allows
the user to swap the sign of the input signal path to eliminate the
need for board-level crossovers in the receiver channel.
Equalization
The ADN4604 receiver incorporates a continuous time equalizer
(EQ) that provides 12 dB of high frequency boost to compensate
up to 40 inches of FR4 at 4.25 Gbps. Each input has an equalizer
control bit. By default, the programmable boost is set to 12 dB.
The boost can be set to 0 dB by programming a Logic 0 to the
respective register bit for the corresponding channel.
Table 7. Equalization Control Registers
EQ[15:0]
0
1
Lane Inversion
The receiver P/N inversion is a feature intended to allow the
user to implement the equivalent of a board-level crossover in
a much smaller area and without additional via impedance
discontinuities that degrade the high frequency integrity of the
signal path. The P/N inversion is available independently for
each of the 16 input channels and is controlled by writing to the
SIGN bit of the RX control registers (Addresses 0x12 and
Address 0x13). Note that using this feature to account for signal
inversions downstream of the receiver requires additional
attention when switching connectivity.
Table 8. Signal Path Polarity Control
SIGN[15:0]
0
1
V
V
TTIx
V
INx
IPx
CC
EE
Figure 40. Simplified Input Circuit
Equalization Boost
0 dB
12 dB (default)
Signal Path Polarity
Noninverting (default)
Inverting
SIMPLIFIED RECEIVER INPUT CIRCUIT
52Ω
RP
RN
52Ω
750Ω
750Ω
R1
R2
R3
1kΩ
Q1
RLN
RL
Q2
I1
RLP
RL