ADN4604ASVZ-RL Analog Devices Inc, ADN4604ASVZ-RL Datasheet - Page 19

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ADN4604ASVZ-RL

Manufacturer Part Number
ADN4604ASVZ-RL
Description
4.25Gbps 16x16 Crossbar Switch
Manufacturer
Analog Devices Inc
Series
XStream™r
Datasheet

Specifications of ADN4604ASVZ-RL

Function
Crosspoint Switch
Circuit
1 x 16:16
On-state Resistance
56 Ohm
Voltage Supply Source
Single Supply
Voltage - Supply, Single/dual (±)
2.7 V ~ 3.6 V
Current - Supply
95mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADN4604ASVZ-RL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
TRANSMITTERS
Output Structure and Output Levels
The ADN4604 transmitter outputs incorporate 50 Ω termin-
ation resistors, ESD protection, and output current switches.
Each channel provides independent control of both the absolute
output level and the preemphasis output level. Note that the
choice of output level affects the output common-mode level.
Preemphasis
Transmission line attenuation can be equalized at the trans-
mitter using preemphasis. The transmit equalizer setting can
be chosen by matching the channel loss to the amount of boost
provided by the preemphasis.
Basic Settings
In the basic mode of operation, predefined preemphasis settings
are available through a lookup table. Each table entry requires
two bytes of memory. The amount of preemphasis provided
is independent of the full-scale current output. Transmitter
preemphasis levels, as well as dc output levels, can be set
through the serial control interface. The output level and
amount of preemphasis can be independently programmed
through advanced registers. By default, however, the total
output amplitude and preemphasis setting space is reduced
to a single table of basic settings that provides eight levels of
output equalization to ease programming for typical FR4
channels.
Table 10 summarizes the absolute output level, preemphasis
level, and high frequency boost for control setting. The full
resolution of eight settings is available through the serial
interface by writing to Bits[2:0] (the TX PE[2:0] bits) of the
Basic TX Control registers shown in Table 11. A single setting
is programmed to all outputs simultaneously by writing to the
0x18 broadcast address.
The TX has four possible output enable states (disabled,
standby, squelched, and enabled) controlled by the TX EN[1:0]
bits as shown in Table 11. Disabled is the lowest power-down
state. When squelched, the output voltage at both P and N
outputs will be the common-mode voltage as defined by the
output current settings. In standby, the output level of both P
and N outputs will be pulled up to the termination supply
(V
TTON
V2
VP
VC
V3
or V
TTOS
V1
VN
).
Figure 42. Simplified TX Output Circuit
I
DC
50Ω
Q1
RP
+ I
PE
IT
Q2
ON-CHIP TERMINATION
RN
50Ω
ESD
V
V
OPx
ONx
V
CC
TTOx
EE
Rev. 0 | Page 19 of 40
The TX CTL SELECT bit (Bit 6) in the TX[15:0] basic control
register determines whether the preemphasis and output
current controls for the channel of interest are selected from
the predefined lookup table or directly from the TX[15:0]
Drive Control[1:0] registers (per channel). Figure 43 is an
illustration of the TX control circuit. Setting the TX CTL
SELECT bit low (default setting) selects preemphasis control
from the predefined, optimized lookup table (Address 0x60
to Address 0x6F).
In applications where the default preemphasis settings in the
lookup table are not sufficient, the lookup table entries can be
modified by programming the TX lookup table registers (0x60
to 0x6F) shown in Table 12. In applications where the eight
table entries are insufficient, each output can be programmed
individually.
Table 10. Preemphasis Boost and Overshoot vs. Setting
PE
Setting
0
1
2
3
4
5
6
7
BASIC SETTINGS
LOOKUP TABLE
ADVANCED SETTINGS
ENTRY 0
ENTRY 1
ENTRY 2
ENTRY 3
ENTRY 4
ENTRY 5
ENTRY 6
ENTRY 7
TABLE
TABLE
TABLE
TABLE
TABLE
TABLE
TABLE
TABLE
OUTPUT LEVEL
PER PORT
Main Tap
Current
(mA)
16
16
16
16
11
8
4
4
Figure 43. Transmitter Control Block Diagram
PE[2:0]
16
16
16
16
16
16
16
16
Delayed Tap
Current (mA)
0
2
5
8
8
8
6
6
16
3
16
IPx
INx
SELECT
TX CTL
Boost
(dB)
0.0
2.0
4.2
6.0
7.8
9.5
12.0
12.0
16
PER OUTPUT PORT
TX EN[1:0]
Overshoot
(%)
0
25
62.5
100
145
200
300
300
TX
2
ADN4604
DC Swing
(mV p-p)
800
800
800
800
550
400
300
300
OPx
ONx

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