ADN4604ASVZ-RL Analog Devices Inc, ADN4604ASVZ-RL Datasheet - Page 20

• Manufacturer Part Number: ADN4604ASVZ-RL
• Description: 4.25Gbps 16x16 Crossbar Switch
• Manufacturer: Analog Devices Inc
• Series: XStream™r

Specifications of ADN4604ASVZ-RL

• Function: Crosspoint Switch
• Circuit: 1 x 16:16
• On-state Resistance: 56 Ohm
• Voltage Supply Source: Single Supply
• Voltage - Supply, Single/dual (±): 2.7 V ~ 3.6 V
• Current - Supply: 95mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADN4604
Table 11 displays the TX Basic Control register. The TX Basic Control register consists of one byte (8 bits) for each of the 16 output
channels. Each TX Basic Control register has the same functionality. The mapping of register address to output channel is shown in the
first column.
Table 11. TX Basic Control Register
Address: Channel
0x18: Broadcast,
0x20: Output 0,
0x21: Output 1,
0x22: Output 2,
0x23: Output 3,
0x24: Output 4,
0x25: Output 5,
0x26: Output 6,
0x27: Output 7,
0x28: Output 8,
0x29: Output 9,
0x2A: Output 10,
0x2B: Output 11,
0x2C: Output 12,
0x2D: Output 13,
0x2E: Output 14,
0x2F: Output 15
Table 12 displays the TX lookup table register. The TX lookup table register consists of two bytes (16 bits) for each of the eight possible
table entries selected by the PE[2:0] field in Table 11. The mapping of table entry to register address is shown in the first column. By
default, the TX Lookup Table register contains the preemphasis settings listed in Table 10, however, these values can be changed for a
flexible selection of output levels and preemphasis boosts. Table 13 lists a variety of possible output level and preemphasis boost settings
and the corresponding TX Drive 0 and TX Drive 1 codes.
Table 12. TX Lookup Table Registers
Address: Channel
0x60: Table Entry 0
0x62: Table Entry 1
0x64: Table Entry 2
0x66: Table Entry 3
0x68: Table Entry 4
0x6A: Table Entry 5
0x6C: Table Entry 6
0x6E: Table Entry 7
0x61: Table Entry 0
0x63: Table Entry 1
0x65: Table Entry 2
0x67: Table Entry 3
0x69: Table Entry 4
0x6B: Table Entry 5
0x6D: Table Entry 6
0x6F: Table Entry 7
Default
0x00
Default
0xFF
0xFF
0xFF
0xFF
0xDC
0xBB
0x99
0x99
0x00
0x99
0xCC
0xFF
0xFF
0xFF
0xDD
0xDD
Register Name
TX basic control
Register Name
TX Lookup
Table Drive 0
TX Lookup
Table Drive 1
Bit
6
5:4
3
2:0
Bit
7
6:4
3
2:0
7
6:4
3
2:0
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Bit Name
DRV EN1
DRV LV1[2:0]
DRV EN0
DRV LV0[2:0]
DRV END
DRV LVD[2:0]
DRV EN2
DRV LV2[2:0]
Bit Name
TX CTL SELECT
TX EN[1:0]
Reserved
PE[2:0]
Description
0: Driver 1 disabled
1: Driver 1 enabled
Driver 1 current = decimal(DRV LV1[2:0]) + 1
0: Driver 0 disabled
1: Driver 0 enabled
Driver 0 current = decimal(DRV LV0[2:0]) + 1
0: Driver D disabled
1: Driver D enabled
Driver D Current = decimal(DRV LVD[2:0]) + 1
0: Driver 2 disabled
1: Driver 2 enabled
Driver 2 current = decimal(DRV LV2[2:0]) + 1
Description
0: PE and output level control is derived from
common lookup table
1: PE and output level control is derived from per port
drive control registers
00: TX disabled, lowest power state
01: TX standby.
10: TX squelched.
11: TX enabled
Reserved. Set to 0.
If TX CTL SELECT = 0, see Table 10
000: Table Entry 0
001: Table Entry 1
010: Table Entry 2
011: Table Entry 3
100: Table Entry 4
101: Table Entry 5
110: Table Entry 6
111: Table Entry 7
If TX CTL SELECT = 1, PE[2:0] are ignored