ADN4604ASVZ-RL Analog Devices Inc, ADN4604ASVZ-RL Datasheet - Page 25

• Manufacturer Part Number: ADN4604ASVZ-RL
• Description: 4.25Gbps 16x16 Crossbar Switch
• Manufacturer: Analog Devices Inc
• Series: XStream™r

Specifications of ADN4604ASVZ-RL

• Function: Crosspoint Switch
• Circuit: 1 x 16:16
• On-state Resistance: 56 Ohm
• Voltage Supply Source: Single Supply
• Voltage - Supply, Single/dual (±): 2.7 V ~ 3.6 V
• Current - Supply: 95mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADN4604
I
To read data from the ADN4604 register set, a microcontroller,
or any other I
signals to the ADN4604 slave device. The steps are listed below;
the signals are controlled by the I
specified. A diagram of the procedure is shown in Figure 47.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Wait for the ADN4604 to acknowledge the request.
11. The ADN4604 then serially transfers the data (eight bits)
12. Acknowledge the data.
2
C DATA READ
Send a start condition (while holding the SCL line high,
pull the SDA line low).
Send the ADN4604 part address (seven bits) whose upper
five bits are the static value b10010 and whose lower two
bits are controlled by the input pins ADDR1 and ADDR0.
This transfer should be MSB first.
Send the write indicator bit (0).
Wait for the ADN4604 to acknowledge the request.
Send the register address (eight bits) from which data is to
be read. This transfer should be MSB first. The register
address is kept in memory in the ADN4604 until the part
is reset or the register address is written over with the same
procedure (Step 1 to Step 6).
Wait for the ADN4604 to acknowledge the request.
Send a repeated start condition (while holding the SCL line
high, pull the SDA line low).
Send the ADN4604 part address (seven bits) whose upper
five bits are the static value b10010 and whose lower two
bits are controlled by the input pins ADDR1 and ADDR0.
This transfer should be MSB first.
Send the read indicator bit (1).
held in the register indicated by the address set in Step 5.
EXAMPLE
SDA
SDA
SCL
2
C master must send the appropriate control
START
1
b10010
2
2
C master, unless otherwise
ADDR
[1:0]
2
R/
W
3
A
4
REGISTER ADDR
5
Figure 47. I
Rev. 0 | Page 25 of 40
2
C Read Diagram
6
A Sr
7
13. Do one or more of the following:
The ADN4604 read process is shown in Figure 47. The SCL
signal is shown along with a general read operation and a
specific example. In the example, Data 0x49 is read from
Address 0x6D of an ADN4604 part with a part address of 0x4B.
The part address is seven bits wide and is composed of the
ADN4604 static upper five bits (b10010) and the pin program-
mable lower two bits (ADDR1 and ADDR0). In this example,
the ADDR1 and ADDR0 bits are set to b01. In Figure 47, the
corresponding step number is visible in the circle under the
waveform. The SCL line is driven by the I
by the ADN4604 slave. As for the SDA line, the data in the
shaded polygons is driven by the ADN4604, whereas the data in
the nonshaded polygons is driven by the I
phase case shown is that of 13a.
Note that the SDA line only changes when the SCL line is low,
except for the case of sending a start, stop, or repeated start
condition, as in Step 1, Step 7, and Step 13. In Figure 47, A is
the same as ACK in Figure 46. Equally, Sr represents a repeated
start where the SDA line is brought high before SCL is raised.
SDA is then dropped while SCL is still high.
b10010
a.
b.
c.
d.
8
Send a stop condition (while holding the SCL line high
Send a repeated start condition (while holding the
SCL line high, pull the SDA line low) and continue
with Step 2 of the write procedure (see the I
Write section) to perform a write.
Send a repeated start condition (while holding the
SCL line high, pull the SDA line low) and continue
with Step 2 of this procedure to perform a read from
another address.
Send a repeated start condition (while holding the
SCL line high, pull the SDA line low) and continue
with Step 8 of this procedure to perform a read from
the same address.
pull the SDA line high) and release control of the bus.
ADDR
[1:0]
8
R/
W
9
A
10
DATA
11
2
2
C master and never
C master. The end
A
12
STOP
13a
2
C Data