ADSP-21060KS-160 Analog Devices Inc, ADSP-21060KS-160 Datasheet
ADSP-21060KS-160
Specifications of ADSP-21060KS-160
Available stocks
Related parts for ADSP-21060KS-160
ADSP-21060KS-160 Summary of contents
Page 1
... DUAL-PORTED SRAM INSTRUCTION TWO INDEPENDENT CACHE DUAL-PORTED BLOCKS 32 48-BIT PROCESSOR PORT ADDR DATA ADDR PROGRAM SEQUENCER 40/32 ALU ADSP-2106x SHARC DSP Microcomputer Family ADSP-21060/ADSP-21060L EMULATION I/O PORT DATA ADDR DATA DATA ADDR EXTERNAL IOD IOA PORT 48 17 ADDR BUS MUX MULTIPROCESSOR ...
Page 2
... Figure 16. Synchronous Read/Write—Bus Slave . . . . . . . . . 24 Figure 17. Multiprocessor Bus Request and Host Bus Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 18a. Synchronous REDY Timing . . . . . . . . . . . . . . 27 Figure 18b. Asynchronous Read/Write—Host to ADSP-2106x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 19a. Three-State Timing (Bus Transition Cycle, SBTS Assertion Figure 19b. Three-State Timing (Host Transition Cycle Figure 20. DMA Handshake Timing . . . . . . . . . . . . . . . . . 31 Figure 21 ...
Page 3
... Mbytes/s ADSP-21060/ADSP-21060L ADSP-21000 FAMILY CORE ARCHITECTURE The ADSP-2106x includes the following architectural features of the ADSP-21000 family core. The ADSP-21060 is code- and function-compatible with the ADSP-21061 and ADSP-21062. Independent, Parallel Computation Units The arithmetic/logic unit (ALU), multiplier and shifter all per- form single-cycle instructions ...
Page 4
... The dual-ported memory and separate on-chip buses allow two data transfers from the core and one from I/O, all in a single cycle. On the ADSP-21060, the memory can be configured as a maxi- mum of 128K words of 32-bit data, 256K words of 16-bit data, 80K words of 48-bit instructions (or 40-bit data), or combina- tions of different word sizes up to four megabits ...
Page 5
... A vector interrupt is provided for interprocessor commands. Maxi- mum throughput for interprocessor data transfer is 240 Mbytes/s over the link ports or external port. Broadcast writes allow simulta- neous transmission of data to all ADSP-2106xs and can be used to implement reflective semaphores. ADSP-21060/ADSP-21060L Link Ports The ADSP-2106x features six 4-bit link ports that provide addi- tional I/O capabilities ...
Page 6
... ADSP-21060/ADSP-21060L 1x CLOCK RESET ADSP-2106x #6 ADSP-2106x #5 ADSP-2106x #4 ADSP-2106x #3 ADDR CLKIN 31-0 DATA 47-0 RESET RPBA 3 011 ID 2-0 CONTROL CPA 4-6 1 ADSP-2106x #2 ADDR CLKIN 31-0 DATA 47-0 RESET RPBA 3 010 ID 2-0 CONTROL CPA 3 ADSP-2106x #1 CLKIN ADDR 31-0 RESET DATA 47-0 RD RPBA WR 3 ACK ...
Page 7
... The same EZ-ICE hardware can be used for the ADSP-21061/ ADSP-21062, to fully emulate the ADSP-21060, with the excep- tion of displaying and modifying the two new SPORTS registers unique to ADSP-21061 ...
Page 8
... I/O/T Memory Write Strobe. This pin is asserted (low) when the ADSP-2106x writes to external memory devices or to the internal memory of other ADSP-2106xs. External devices must assert WR to write to the ADSP-2106x’s internal memory multiprocessing system WR is output by the bus master and is input by all other ADSP-2106xs. ...
Page 9
... Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor bus arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system con- figuration selection which must be set to the same value on every ADSP-2106x. If the value of RPBA is changed during system operation, it must be changed in the same CLKIN cycle on every ADSP-2106x. ...
Page 10
... TRST Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power- I held low for proper operation of the ADSP-2106x. TRST has a 20 kΩ internal pull-up resistor. EMU (O/D) O Emulation Status. Must be connected to the ADSP-2106x EZ-ICE target board connector only. ...
Page 11
... BTCK up to VDD. The TRST pin must be asserted after power-up (through BTRST on the connector) or held low for proper operation of the ADSP-2106x. None of the Bxxx pins (Pins 11) are connected on the EZ-ICE probe. The JTAG signals are terminated on the EZ-ICE probe as ...
Page 12
... Connecting CLKIN to Pin 4 of the EZ-ICE header is optional. The emulator only uses CLKIN when directed to perform operations such as starting, stopping and single-stepping mul- tiple ADSP-21061 in a synchronous manner. If you do not need these operations to occur synchronously on the multiple proces- sors, simply tie Pin 4 of the EZ-ICE header to ground. ...
Page 13
... V 4 TIMEXP, HBG, REDY, DMAG1, 3-0 , LxCLK, LxACK, BMS, TDO, EMU, ICSA. 3-0 , REDY, HBG, DMAG1, DMAG2, BMS, BR 3-0 = 001 and another ADSP-21060 is 2-0 = 001 and another 2-0 Units V ° RPBA, 2-0 Units V V µA µ ...
Page 14
... composite average based on a range of high activity code. I DDINHIGH 3 Idle denotes ADSP-21060L state during execution of IDLE instruction. only. See the Power Dissipation section of this data sheet for calcula High Activity (I DDINPEAK ...
Page 15
... V 4 TIMEXP, HBG, REDY, DMAG1, 3-0 , LxCLK, LxACK, BMS, TDO, EMU, ICSA. 3-0 , REDY, HBG, DMAG1, DMAG2, BMS, BR 3-0 = 001 and another ADSP-21060 is 2-0 = 001 and another 2-0 Units V ° RPBA, 2-0 Units V V µA µ ...
Page 16
... composite average based on a range of high activity code. I DDINHIGH 3 Idle denotes ADSP-21060L state during execution of IDLE instruction. only. See the Power Dissipation section of this data sheet for calcula High Activity (I DDINPEAK ...
Page 17
... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-2106x features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
Page 18
... Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required for multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic synchronizes itself automatically after reset. ...
Page 19
... RD, WR FLAG INPUT ADSP-21060 Min Max 15 ADSP-21060 Min Max 5DT/ – 5DT/ 7DT/ Enable 3 OUT Disable 14 OUT t DFO t DFO t HFO FLAG OUTPUT t HFI t SFI t HFIWR ADSP-21060/ADSP-21060L ADSP-21060L Min Max 15 t DTEX ADSP-21060L Min Max 8 + 5DT/16 0 – 5DT/ 7DT/ DFOD Units ns Units ...
Page 20
... ADSP-21060/ADSP-21060L Memory Read—Bus Master Use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-2106x is the bus master accessing external memory space. These switching Parameter Timing Requirements: t Address, Selects Delay to Data Valid ...
Page 21
... Memory Write—Bus Master Use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-2106x is the bus master accessing external memory space. These switching Parameter Timing Requirements: t ACK Delay from Address, Selects ...
Page 22
... When accessing a slave ADSP-2106x, these switching character- istics must meet the slave’s timing requirements for synchronous read/writes (see Synchronous Read/Write—Bus Slave). The slave ADSP-2106x must also meet these (bus master) timing requirements for data and acknowledge setup and hold times. ADSP-21060 ...
Page 23
... CLKIN t DADCCK ADRCLK t DADRO ADDRESS MSx DPGC PAGE ACK (IN) READ CYCLE t DRWL RD DATA (IN) WRITE CYCLE t DRWL WR t SDDATO DATA (OUT) ADSP-21060/ADSP-21060L t ADRCK t ADRCKH t DAAK t SACKC t SSDATI t ADRCKL t HADRO t HACK t DRDO t HSDATI t DWRO t DATTR ...
Page 24
... ADSP-21060/ADSP-21060L Synchronous Read/Write—Bus Slave Use these specifications for ADSP-2106x bus master accesses of a slave’s IOP registers or internal memory (in multiprocessor Parameter Timing Requirements: Address, SW Setup before CLKIN t SADRI Address, SW Hold before CLKIN t HADRI RD/WR Low Setup before CLKIN t SRWLI RD/WR Low Hold after CLKIN ...
Page 25
... NOTES 1 For first asynchronous access after HBR and CS asserted, ADDR low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the ADSP-2106x” section in the ADSP-2106x SHARC User’s Manual, Second Edition. 2 Only required for recognition in the current cycle. ...
Page 26
... ADSP-21060/ADSP-21060L CLKIN t SHBRI HBR HBG (OUT) BRx (OUT) CPA (OUT) (O/D) HBG (IN) BRx (IN) CPA (IN) (O/D) t SRPBAI RPBA HBR AND CS t DRDYCS REDY (O/D) REDY (A/D) HBG (OUT O/D = OPEN DRAIN, A/D = ACTIVE DRIVE t HHBRI t DHBGO t HHBGO t DBRO t HBRO t DCPAO t SHBGI t SBRI ...
Page 27
... WR goes low after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Proces- HBGRCSV sor Control of the ADSP-2106x” section in the ADSP-2106x SHARC User’s Manual, Second Edition. CLKIN REDY (O/D) REDY (A/D) drive the RD and WR pins to access the ADSP-2106x’ ...
Page 28
... ADSP-21060/ADSP-21060L READ CYCLE ADDRESS/CS RD DATA (OUT) REDY (O/D) REDY (A/D) WRITE CYCLE ADDRESS CS WR DATA (IN) REDY (O/D) REDY (A/D) O/D = OPEN DRAIN, A/D = ACTIVE DRIVE t SADRDL t SDATRDY t t DRDYRDL RDYPRD t SCSWRL t WWRL t SDATWH t t RDYPWR DRDYWRL t HADRDH t WRWH t HDARWH t DRDHRDY t t HADWRH ...
Page 29
... DT t STSCK t HTSCK t t MIENS, MIENHG t DATEN t ACKEN t MENHBG ADSP-21060/ADSP-21060L ADSP-21060L Min Max DT/2 –1.25 – DT/8 –1.5 – DT/8 –1.5 – DT/8 0 – DT/4 1.5 – DT/4 2.0 – DT 5DT/16 0 – DT/8 7 – DT/8 7.5 + DT/4 –1 – DT/8 6 – DT/8 – ...
Page 30
... DT DT 3DT 5DT/8 –2 – DT/8 6 – DT 9DT/ 5DT DT/ DT/ 9DT/ 3DT –0 RD, WR and ACK 31-0 3-0 , RD, WR, 31-0 , and ACK also apply. 47-0 ADSP-21060L Min Max Units 5DT 7DT 7DT DT DT 3DT 5DT/8 ns –2 – DT/8 6 – DT 9DT/ ...
Page 31
... CLKIN t SDRLC DMARx DMAGx TRANSFERS BETWEEN ADSP-2106x INTERNAL MEMORY AND EXTERNAL DEVICE DATA (FROM ADSP-2106x TO EXTERNAL DRIVE) DATA (FROM EXTERNAL DRIVE TO ADSP-2106x) TRANSFERS BETWEEN EXTERNAL DEVICE AND EXTERNAL MEMORY* (EXTERNAL HANDSHAKE MODE) WR (EXTERNAL DEVICE TO EXTERNAL MEMORY) RD (EXTERNAL MEMORY TO EXTERNAL DEVICE) ADDRESS ...
Page 32
... Only required for interrupt recognition in the current cycle. ADSP-21060 Min Max 3 DT/2 28.5 + DT/2 1 – DT DT/2 18 –7 15.5 3 –3 (t /2) – / /2) – / × /2) + 8 ADSP-21060L Min Max Units DT/2 28.5 + DT/2 ns – DT DT –7 ns 16.5 ns 2.5 ns – /2) – / /2) – 1.25 (t /2) + 1.0 ...
Page 33
... The setup and hold skew times shown below are calculated to include only one tester guardband. ADSP-21060 Setup Skew = 1.93 ns max ADSP-21060 Hold Skew = 2.95 ns max ADSP-21060L Setup Skew = 1.87 ns max ADSP-21060L Hold Skew = 1.69 ns max Parameter Receive Timing Requirements: t ...
Page 34
... ADSP-21060/ADSP-21060L TRANSMIT CLKIN t DLCLK t t LCLKTWH LCLKTWL LCLK 1x OR LCLK 2x t DLDCH t HLDCH LDAT(3:0) OUT LACK (IN) t THE REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED. SLACH RECEIVE CLKIN t LCLKRWH LCLK 1x OR LCLK 2x LDAT(3:0) t DLAHC LACK (OUT) ...
Page 35
... SCLK width. ADSP-21060 Min Max 4.5 –1 /2) – / SCLK SCLK 3 3 3DT ADSP-21060/ADSP-21060L ADSP-21060L Min Max 3.5 4 1 4.5 –1.5 7 /2) – 2.5 (t /2) + 2.5 SCLK SCLK 4.0 10 3DT 12.8 3.5 Units ...
Page 36
... ADSP-21060/ADSP-21060L NOTES 1 Referenced to sample edge. 2 RFS hold after RCK when MCE = 1, MFD = minimum from drive edge. TFS hold after TCK for late external TFS minimum from drive edge. 3 Referenced to drive edge. 4 Applies only to gated serial clock mode used for serial port system I/O in mesh multiprocessing systems. ...
Page 37
... EXTERNAL RFS with MCE = 1, MFD = 0 DRIVE SAMPLE DRIVE RCLK t HOFSE/I t SFSE/ I RFS DDTENFS HDTE/I DT 1ST BIT t DDTLFSE LATE EXTERNAL TFS DRIVE SAMPLE DRIVE TCLK t HOFSE/I t SFSE/ I TFS t DDTE DDTENFS HDTE 1ST BIT t DDTLFSE ADSP-21060/ADSP-21060L (SEE NOTE 2) DDTE/I 2ND BIT (SEE NOTE 2) 2ND BIT ...
Page 38
... ADSP-21060 Min Max 18.5 , LxCLK, LxACK, EBOOT, LBOOT, BMS, CLKIN, RESET. 3-0 , LxCLK, LxACK, BMS. 3-0 t TCK t t STAP HTAP t DTDO t SSYS t DSYS ADSP-21060L Min Max Units 18 18 RPBA, IRQ , ID , FLAG , DR0, DR1, 6-1 2-0 2-0 3-0 , CPA, FLAG , TIMEXP, DT0, ...
Page 39
... OUTPUT DRIVE CURRENTS Figure 28 shows typical I-V characteristics for the output drivers of the ADSP-2106x. The curves represent the current drive capability of the output drivers as a function of output voltage. POWER DISSIPATION Total power dissipation has two components, one due to inter- nal circuitry and one due to the switching of external output drivers ...
Page 40
... To determine the data output hold time in a particular system, using the equation given above. Choose ∆V first calculate t DECAY to be the difference between the ADSP-2106x’s output voltage and the input threshold for the device requiring the hold time. A typical ∆V will be 0 the total bus capacitance (per ...
Page 41
... –20 –40 –60 –80 –100 –120 160 180 200 160 180 200 0 20 ADSP-21060/ADSP-21060L Y = 0.03X –1. 100 125 150 175 LOAD CAPACITANCE – pF ° 3.3V, +25 C ° 3.6V, – ° 3.0V, +85 C ° 3.3V, +25 C ° 3.6V, – 0 ...
Page 42
... Note that the copper slug is internally connected to GND through the device substrate. The ADSP-21060KB and ADSP- 21060LKB are plastic ball grid arrays. The θ package is 1.7°C/Q. The ADSP-2106x is specified for a case temperature (T To ensure that the T data sheet specification is not ex- CASE ceeded, a heatsink and/or an air flow source may be used ...
Page 43
... VDD 156 GND 117 DATA44 157 DATA17 118 DATA43 158 DATA16 119 DATA42 159 DATA15 120 GND 160 VDD ADSP-21060/ADSP-21060L 180 121 Pin Pin Pin Pin No. Name No. Name 201 L2DAT0 161 DATA14 202 L2CLK 162 DATA13 203 L2ACK 163 DATA12 204 NC ...
Page 44
... ADSP-21060/ADSP-21060L 0.030 (0.75) 0.024 (0.60) TYP 0.020 (0.50) SEATING PLANE LEAD PITCH 0.01969 (0.50) LEAD WIDTH 0.011 (0.27) 0.009 (0.22) TYP 0.007 (0.17) 0.003 (0.08) 0.010 (0.25) PACKAGE DIMENSIONS Dimensions shown in inches and (mm). 240-Lead MQFP 1.372 (34.85) 1.362 (34.60) TYP SQ 1.352 (34.35) 1 ...
Page 45
... BR4 C11 F11 GND C12 DATA46 F12 DATA29 C13 DATA41 F13 DATA26 C14 DATA38 F14 DATA28 C15 DATA36 F15 DATA27 ADSP-21060/ADSP-21060L Ball # Name Ball # G01 ADDR14 K01 G02 ADDR15 K02 G03 ADDR16 K03 G04 ADDR19 K04 G05 GND K05 G06 VDD ...
Page 46
... ADSP-21060/ADSP-21060L 225-Plastic Ball Grid Array (PBGA) Package Pinout BR3 DATA42 DATA44 DATA47 PAGE DATA39 DATA43 DATA45 BR2 BR6 DATA36 DATA38 DATA41 DATA46 DATA34 DATA35 DATA37 DATA40 DATA31 DATA32 DATA30 DATA33 DATA27 DATA28 DATA26 DATA29 GND DATA23 DATA24 DATA25 DATA22 GND DATA20 ...
Page 47
... ACTUAL POSITION OF EACH BALL IS WITHIN 0.004 (0.10) OF ITS IDEAL POSITION RELATIVE TO THE BALL GRID. Case Part Temperature Number Range ADSP-21060KS-133 0°C to +85°C ADSP-21060KS-160 0°C to +85°C ADSP-21060KB-160 0°C to +85°C ADSP-21060LKS-133 0°C to +85°C ADSP-21060LKS-160 0°C to +85°C ADSP-21060LKB-160 0° ...