ADSP-21060KS-160 Analog Devices Inc, ADSP-21060KS-160 Datasheet - Page 3

• Manufacturer Part Number: ADSP-21060KS-160
• Description: Digital Signal Processor IC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21060KS-160

• Supply Voltage Max: 5.25V
• Dsp Type: Fixed / Floating Point
• Mounting Type: Surface Mount
• Package / Case: 240-MQFP
• Memory Organization - Ram: 4M
• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: 0°C ~ 85°C
• Device Core Size: 32b
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 40MHz
• Mips: 40
• Device Input Clock Speed: 40MHz
• Ram Size: 512KB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: MQFP
• Lead Free Status / Rohs Status: Not Compliant

S
GENERAL DESCRIPTION
The ADSP-21060 SHARC—Super Harvard Architecture Com-
puter—is a signal processing microcomputer that offers new
capabilities and levels of performance. The ADSP-2106x
SHARCs are 32-bit processors optimized for high performance
DSP applications. The ADSP-2106x builds on the ADSP-
21000 DSP core to form a complete system-on-a-chip, adding a
dual-ported on-chip SRAM and integrated I/O peripherals sup-
ported by a dedicated I/O bus.
Fabricated in a high speed, low power CMOS process, the
ADSP-2106x has a 25 ns instruction cycle time and operates
at 40 MIPS. With its on-chip instruction cache, the processor
can execute every instruction in a single cycle. Table I shows
performance benchmarks for the ADSP-2106x.
The ADSP-2106x SHARC represents a new standard of inte-
gration for signal computers, combining a high performance
floating-point DSP core with integrated, on-chip system features
including a 4 Mbit SRAM memory host processor interface,
DMA controller, serial ports, and link port and parallel bus
connectivity for glueless DSP multiprocessing.
Figure 1 shows a block diagram of the ADSP-2106x, illustrating
the following architectural features:
Figure 2 shows a typical single-processor system. A multi-
processing system is shown in Figure 3.
1024-Pt. Complex FFT
FIR Filter (per Tap)
IIR Filter (per Biquad)
Divide (y/x)
Inverse Square Root (1/√x)
DMA Transfer Rate
Table I. ADSP-21060/ADSP-21060L Benchmarks (@ 40 MHz)
Computation Units (ALU, Multiplier and Shifter) with a
Data Address Generators (DAG1, DAG2)
Program Sequencer with Instruction Cache
Interval Timer
On-Chip SRAM
External Port for Interfacing to Off-Chip Memory and
Host Port and Multiprocessor Interface
DMA Controller
Serial Ports and Link Ports
JTAG Test Access Port
(Radix 4, with Digit Reverse)
Shared Data Register File
Peripherals
0.46 ms
25 ns
100 ns
150 ns
225 ns
240 Mbytes/s
18,221 cycles
1 cycle
4 cycles
6 cycles
9 cycles
ADSP-21000 FAMILY CORE ARCHITECTURE
The ADSP-2106x includes the following architectural features
of the ADSP-21000 family core. The ADSP-21060 is code- and
function-compatible with the ADSP-21061 and ADSP-21062.
Independent, Parallel Computation Units
The arithmetic/logic unit (ALU), multiplier and shifter all per-
form single-cycle instructions. The three units are arranged in
parallel, maximizing computational throughput. Single multi-
function instructions execute parallel ALU and multiplier opera-
tions. These computation units support IEEE 32-bit single-
precision floating-point, extended precision 40-bit floating-
point, and 32-bit fixed-point data formats.
Data Register File
A general purpose data register file is used for transferring data
between the computation units and the data buses, and for
storing intermediate results. This 10-port, 32-register (16 pri-
mary, 16 secondary) register file, combined with the ADSP-
21000 Harvard architecture, allows unconstrained data flow
between computation units and internal memory.
Single-Cycle Fetch of Instruction and Two Operands
The ADSP-2106x features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see Figure 1). With its separate program and data memory
buses and on-chip instruction cache, the processor can simulta-
neously fetch two operands and an instruction (from the cache),
all in a single cycle.
(6 MAXIMUM)
(OPTIONAL)
(OPTIONAL)
(OPTIONAL)
1x CLOCK
DEVICES
DEVICE
SERIAL
SERIAL
DEVICE
LINK
3
4
CLKIN
EBOOT
LBOOT
IRQ
FLAG
TIMEXP
LxCLK
LxACK
LxDAT
RPBA
ID
TCLK0
RCLK0
TFS0
RSF0
DT0
DR0
TCLK1
RCLK1
TFS1
RFS1
DT1
DR1
ADSP-21060/ADSP-21060L
2-0
RESET
ADSP-2106x
2-0
3-0
3-0
ADDR
DATA
DMAR1-2
DMAG1-2
ADRCLK
JTAG
REDY
BR
MS
PAGE
SBTS
HBG
HBR
CPA
BMS
ACK
47-0
WR
31-0
SW
CS
7
RD
1-6
3-0
CS
ADDR
DATA
ADDR
DATA
OE
WE
ACK
CS
DATA
ADDR
DATA
PROCESSOR
DMA DEVICE
INTERFACE
(OPTIONAL)
PERIPHERALS
(OPTIONAL)
(OPTIONAL)
MEMORY
(OPTIONAL)
HOST
EPROM
AND
BOOT