ADSP-21060KS-160 Analog Devices Inc, ADSP-21060KS-160 Datasheet - Page 39

• Manufacturer Part Number: ADSP-21060KS-160
• Description: Digital Signal Processor IC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21060KS-160

• Supply Voltage Max: 5.25V
• Dsp Type: Fixed / Floating Point
• Mounting Type: Surface Mount
• Package / Case: 240-MQFP
• Memory Organization - Ram: 4M
• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: 0°C ~ 85°C
• Device Core Size: 32b
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 40MHz
• Mips: 40
• Device Input Clock Speed: 40MHz
• Ram Size: 512KB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: MQFP
• Lead Free Status / Rohs Status: Not Compliant

OUTPUT DRIVE CURRENTS
Figure 28 shows typical I-V characteristics for the output drivers
of the ADSP-2106x. The curves represent the current drive
capability of the output drivers as a function of output voltage.
POWER DISSIPATION
Total power dissipation has two components, one due to inter-
nal circuitry and one due to the switching of external output
drivers. Internal power dissipation is dependent on the instruc-
tion execution sequence and the data operands involved. Inter-
nal power dissipation is calculated in the following way:
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
and is calculated by:
The load capacitance should include the processor’s package
capacitance (C
load high and then back low. Address and data pins can drive
high and low at a maximum rate of 1/(2t
can switch every cycle at a frequency of 1/t
at 1/(2t
Example:
Estimate P
The P
drive:
Pin
Type
Address
MS0
WR
Data
ADDRCLK 1
– the number of output pins that switch during each cycle (O)
– the maximum frequency at which they can switch (f)
– their load capacitance (C)
– their voltage swing (V
–A system with one bank of external data memory RAM (32-bit)
–Four 128K × 8 RAM chips are used, each with a load of 10 pF
–External data memory writes occur every other cycle, a rate
–The instruction cycle rate is 40 MHz (t
of 1/(4t
Table II. External Power Calculations (5 V Device)
EXT
CK
), but selects can switch on each cycle.
equation is calculated for each class of pins that can
CK
EXT
# of
Pins
15
1
1
32
), with 50% of the pins switching
with the following assumptions:
IN
). The switching frequency includes driving the
%
Switching
50
0
–
50
–
P
EXT
P
INT
= O × C × V
DD
× 44.7 pF × 10 MHz × 25 V
× 44.7 pF × 10 MHz × 25 V
× 44.7 pF × 20 MHz × 25 V
× 14.7 pF × 10 MHz × 25 V
× 4.7 pF
)
= I
C
DDIN
× V
DD
× 20 MHz × 25 V
f
2
DD
CK
× f
CK
). The write strobe
CK
. Select pins switch
= 25 ns).
V
DD
P
EXT
2
= P
= 0.084 W
= 0.000 W
= 0.022 W
= 0.059 W
= 0.002 W
= 0.167 W
EXT
Pin
Type
Address
MS0
WR
Data
ADDRCLK 1
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:
Note that the conditions causing a worst-case P
from those causing a worst-case P
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching simultaneously.
TEST CONDITIONS
Output Disable Time
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from
their output high or low voltage. The time for the voltage on the
bus to decay by ∆V is dependent on the capacitive load, C
the load current, I
the following equation:
The output disable time t
and t
interval from when the reference signal switches to when the
output voltage decays ∆V from the measured output high or
output low voltage. t
I
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start
driving. The output enable time t
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram (Figure 25). If multiple
pins (such as the data bus) are enabled, the measurement value
is that of the first pin to start driving.
L
, and with ∆V equal to 0.5 V.
Table III. External Power Calculations (3.3 V Device)
DECAY
# of
Pins
15
1
1
32
as shown in Figure 25. The time t
P
ADSP-21060/ADSP-21060L
TOTAL
%
Switching
50
0
–
50
–
L
. This decay time can be approximated by
DECAY
= P
t
DECAY
DIS
EXT
is calculated with test loads C
× 44.7 pF × 10 MHz × 10.9 V = 0.037 W
× 44.7 pF × 10 MHz × 10.9 V = 0.000 W
× 44.7 pF × 20 MHz × 10.9 V = 0.010 W
× 14.7 pF × 10 MHz × 10.9 V = 0.026 W
× 4.7 pF
is the difference between t
C
+ (I
=
ENA
INT
C
DDIN2
L
I
. Maximum P
L
∆V
is the interval from when a
× 20 MHz × 10.9 V = 0.001 W
× 5.0 V )
f
EXT
MEASURED
V
INT
DD
P
are different
EXT
2
cannot
MEASURED
= P
= 0.074 W
L
is the
L
and
EXT
and