ADSP-21060KS-160 Analog Devices Inc, ADSP-21060KS-160 Datasheet - Page 21

• Manufacturer Part Number: ADSP-21060KS-160
• Description: Digital Signal Processor IC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21060KS-160

• Supply Voltage Max: 5.25V
• Dsp Type: Fixed / Floating Point
• Mounting Type: Surface Mount
• Package / Case: 240-MQFP
• Memory Organization - Ram: 4M
• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: 0°C ~ 85°C
• Device Core Size: 32b
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 40MHz
• Mips: 40
• Device Input Clock Speed: 40MHz
• Ram Size: 512KB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: MQFP
• Lead Free Status / Rohs Status: Not Compliant

Memory Write—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-2106x is
the bus master accessing external memory space. These switching
Parameter
Timing Requirements:
t
t
Switching Characteristics:
t
t
t
t
t
t
t
t
t
t
W = (number of wait states specified in WAIT register) × t
H = t
I = t
NOTES
1
2
3
ACK Delay/Setup: User must meet t
The falling edge of MSx, SW, BMS is referenced.
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
DAAK
DSAK
DAWH
DAWL
WW
DDWH
DWHA
DATRWH
WWR
DDWR
WDE
SADADC
tion of ACK (High).
CK
CK
(if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
(if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
ACK Delay from Address, Selects
ACK Delay from WR Low
Address, Selects to WR Deasserted
Address, Selects to WR Low
WR Pulsewidth
Data Setup before WR High
Address Hold after WR Deasserted
Data Disable after WR Deasserted
WR High to WR, RD, DMAGx Low
Data Disable before WR or RD Low
WR Low to Data Enabled
Address, Selects to ADRCLK High
RD , DMAG
ADDRESS
MSx , SW
ADRCLK
DATA
(OUT)
BMS
ACK
WR
DAAK
t
SADADC
or t
1
t
DAWL
2
DSAK
or synchronous specification t
t
1, 2
3
DAAK
2
2
CK
Min
17 + 15DT/16 + W
3 + 3DT/8
12 + 9DT/16 + W
7 + DT/2 + W
0.5 + DT/16 + H
1 + DT/16 + H
8 + 7DT/16 + H
5 + 3DT/8 + I
–1 + DT/16
0 + DT/4
.
t
DSAK
t
WDE
ADSP-21060
t
DAWH
SACKC
t
characteristics also apply for bus master synchronous read/write
timing (see Synchronous Read/Write–Bus Master). If these
timing requirements are met, the synchronous read/write timing
can be ignored (and vice versa).
Max
14 + 7DT/8 + W
8 + DT/2 + W
6 + DT/16 + H
WW
for deassertion of ACK (Low), all three specifications must be met for asser-
t
DDWH
ADSP-21060/ADSP-21060L
Min
17 + 15DT/16 + W
3 + 3DT/8
12 + 9DT/16 + W
7 + DT/2 + W
0.5 + DT/16 + H
1 + DT/16 + H
8 + 7DT/16 + H
5 + 3DT/8 + I
–1 + DT/16
0 + DT/4
ADSP-21060L
t
DATRWH
t
DWHA
t
WWR
Max
14 + 7DT/8 + W
8 + DT/2 + W
6 + DT/16 + H
t
DDWR
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns