ADUC7033BSTZ-88-RL Analog Devices Inc, ADUC7033BSTZ-88-RL Datasheet - Page 62

• Manufacturer Part Number: ADUC7033BSTZ-88-RL
• Description: Flash 96k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BSTZ-88-RL

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7033
Figure 27. Typical Digital Filter Response at f
In general, it is possible to program different values of SF and
AF in the ADCFLT register and achieve the same ADC update
rate. In practical terms, the trade-off with any value of ADCFLT
is frequency response vs. ADC noise. For optimum filter response
and ADC noise when using combinations of SF and AF, best
practice suggests choosing an SF in the range of 16 decimal to
40 decimal, or 0x10 to 0x28, and then increasing the AF value
to achieve the required ADC throughput. Table 43 shows some
common ADCFLT configurations.
Table 43. Common ADCFLT Configurations
ADC Mode
Normal
Normal
Normal
Normal
Normal
Normal
Low Power
Low Power
Low Power
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0
2
4
SF
0x1D
0x1F
0x07
0x07
0x03
0x00
0x10
0x10
0x1F
6
FREQUENCY (kHz)
8
10
12
ADC
AF
0x3F
0x16
0x00
0x00
0x00
0x00
0x03
0x09
0x3D
= 1 Hz (ADCFLT = 0xBD1F)
14
16
18
20
Other Config
Chop On
Chop On
None
Sinc3 Modify
Running Average
Running Average
Chop On
Chop On
Chop On
Rev. B | Page 62 of 140
ADC Calibration
As shown in detail in the top level diagrams (Figure 17 and
Figure 18), the signal flow through all ADC channels can be
described in simple steps.
1.
2.
3.
4.
5.
6.
Each ADC has a specific offset and gain correction or calibra-
tion coefficient associated with it that are stored in MMR-based
offset and gain registers (ADCxOF and ADCxGN). The offset
and gain registers can be used to remove offsets and gain errors
arising within the part as well as system level offset and gain
errors external to the part.
These registers are configured at power-on with a factory
programmed calibration value. These factory calibration values
vary from part to part, reflecting the manufacturing variability
of internal ADC circuits. However, these registers can also be
overwritten by user code (only if the ADC is in idle mode) and
are automatically overwritten if an offset or gain calibration
cycle is initiated by the user through the mode bits in the
ADCMDE[2:0] MMR. Two types of automatic calibration are
available to the user, namely, self-calibration and system
calibration.
ADCFLT
0xBF1D
0x961F
0x0007
0x0087
0x4003
0x4000
0x8310
0x8910
0xBD1F
An input voltage is applied through an input buffer (and
PGA in the case of the I-ADC) to the Σ-Δ modulator.
The modulator output is applied to a programmable digital
decimation filter.
The filter output result is then averaged if chopping is used.
An offset value (ADCxOF) is subtracted from the result.
This result is scaled by a gain value (ADCxGN).
Finally, the result is formatted as twos complement/offset
binary, rounded to 16 bits, or clamped to ±full scale.
f
4 Hz
10 Hz
1 kHz
1 kHz
2 kHz
8 kHz
20 Hz
10 Hz
1 Hz
ADC
t
0.5 sec
0.2 sec
3 ms
3 ms
2 ms
0.5 ms
100 ms
200 ms
2 sec
SETTLE