ADUC7033BSTZ-88-RL Analog Devices Inc, ADUC7033BSTZ-88-RL Datasheet - Page 66

• Manufacturer Part Number: ADUC7033BSTZ-88-RL
• Description: Flash 96k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BSTZ-88-RL

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7033
SYSTEM CLOCKS
The ADuC7033 integrates a very flexible clocking system that
can be clocked from one of three sources: an integrated on-chip
precision oscillator, an integrated on-chip low power oscillator,
or an external watch crystal. These three options are shown in
Figure 29.
Each of the internal oscillators are divided by four to generate a
clock frequency of 32.768 kHz. The PLL locks onto a multiple
(625) of 32.768 kHz, supplied by either of the internal oscillators
or the external crystal, to provide a stable 20.48 MHz clock for
the system. The core can operate at this frequency, or at binary
submultiples of it, thereby allowing power saving when peak
performance is not required.
By default, the PLL is driven by the low power oscillator that
generates a 20.48 MHz clock source. The ARM7TDMI core is
OSCILLATOR
PRECISION
CLOCK
CORE
CORE CLOCK
PLL OUTPUT
(20.48MHz)
1
8
PLL LOCK
PRECISION
MCU
131kHz
2
DIV 4
CD
1
EXTERNAL
32.768kHz
SPI
PRECISION
32.768kHz
EXTERNAL CRYSTAL
CONTROLLER
PLL OUTPUT
(OPTIONAL)
CIRCUITRY
Figure 29. ADuC7033 System Clock Generation
CRYSTAL
20.48MHz
PLLCON
FLASH
CORE CLOCK
PLL
LOW POWER
32.768kHz
LOW POWER
OSCILLATOR
Rev. B | Page 66 of 140
ECLK 2.5MHz
CLOCK
ADC
DIVIDER
CLOCK
LOW POWER
UART
131kHz
ADCMDE
DIV 4
ADC
driven by a CD divided clock derived from the output of the PLL.
By default, the CD divider is configured to divide the PLL
output by two, thereby generating a core clock of 10.24 MHz.
The divide factor can be modified to generate a binary weighted
divider factor from 1 to 128 that can be altered dynamically by
user code.
The ADC is driven by the output of the PLL, divided to give an
ADC clock source of 512 kHz. In low power mode, the ADC
clock source is switched from the standard 512 kHz to the low
power 131 kHz oscillator.
Note that the low power oscillator drives both the watchdog and
core wake-up timers through a divide-by-four circuit. A detailed
block diagram of the ADuC7033 clocking system is shown in
Figure 29.
CORE CLOCK
CORE CLOCK
CORE CLOCK
CORE CLOCK
OSCILLATOR
LOW POWER
LOW POWER
LOW POWER
LOW POWER
LOW POWER
LOW POWER
LOW POWER
PLL OUTPUT
PRECISION
EXTERNAL
EXTERNAL
PRECISION
EXTERNAL
PRECISION
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
GPIO_5
GPIO_8
131kHz
(5MHz)
SYNCHRONIZATION
HIGH ACCURCY
CALIBRATION
CALIBRATION
LOW POWER
WATCHDOG
COUNTER
COUNTER
LIFE TIME
WAKE-UP
TIMER 0
TIMER 1
TIMER 2
TIMER 3
TIMER 4
LIN H/W
STI