ADUC7033BSTZ-88-RL Analog Devices Inc, ADUC7033BSTZ-88-RL Datasheet - Page 67

• Manufacturer Part Number: ADUC7033BSTZ-88-RL
• Description: Flash 96k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BSTZ-88-RL

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The operating mode, clocking mode, and programmable clock
divider are controlled using two MMRs, PLLCON and POWCON,
and the status of the PLL is indicated by PLLSTA. PLLCON
controls the operating mode of the clock system and POWCON
controls both the core clock frequency and the power-down
mode. PLLSTA indicates the presence of an oscillator on the
XTAL1 pin, the PLL lock status, and the PLL interrupt.
It is recommended that before powering down the ADuC7033,
switch the clock source for the PLL to the low power 131 kHz
oscillator to reduce wake-up time. The low power oscillator is
always active.
When the ADuC7033 wakes up from power-down, the MCU
core begins executing code as soon as the PLL begins oscillating.
This occurs before the PLL has locked to a frequency of
20.48 MHz. To ensure the Flash/EE memory controller is
executing with a valid clock, the controller is driven with a PLL
output divided by eight clock source while the PLL is locking.
When the PLL locks, the PLL output is switched from the PLL
output divided by eight to the locked PLL output.
POWKEY0
POWCON
POWKEY1
iA1*iA2;
PLLKEY0
PLLCON
PLLKEY1
iA1*iA2;
PLLSTA Register
Name:
Address:
Default Value:
Access:
Function:
Table 44. PLLSTA MMR Bit Designations
Bit
31 to 3
2
1
0
=
=
=
=
=
=
PLLSTA
0xFFFF0400
N/A
Read only
This 8-bit register allows user code to monitor the lock state of the PLL and the status of the external crystal.
Description
Reserved.
XTAL Clock, Read Only. This is a live representation of the current logic level on XTAL1. It allows the user to check to see
if an external clock source is present. If present, this bit alternates high and low at a frequency of 32.768 kHz.
PLL Lock Status Bit, Read Only.
Set when the PLL is locked and outputting 20.48 MHz.
Clear when the PLL is not locked and outputting an f
PLL Interrupt.
Set if the PLL lock status bit signal goes low.
Cleared by writing 1 to this bit.
0x01; //POWCON KEY
0x00; //Full Power-down
0xF4; //POWCON KEY
0xAA;
0x0;
0x55; //PLLCON KEY
//dummy cycle to clear the pipe line, where iA1 and iA2 are defined
//PLLCON KEY
//Switch to Low Power Osc.
//dummy cycle to prevent Flash/EE memory access during clock change
as longs and are not 0
Rev. B | Page 67 of 140
CORE
If user code requires an accurate PLL output, user code must
poll the Lock Status Bit PLLSTA[1] after wake-up before
resuming normal code execution.
The PLL is locked within 2 ms if the PLL is clocked from an
active clock source, such as a low power 131 kHz oscillator, after
waking up.
PLLCON is a protected MMR with two 32-bit keys: PLLKEY0
(prewrite key) and PLLKEY1 (postwrite key).
PLLKEY0 = 0x000000AA
PLLKEY1 = 0x00000055
POWCON is a protected MMR with two 32-bit keys:
POWKEY0 (prewrite key) and POWKEY1 (postwrite key).
POWKEY0 = 0x00000001
POWKEY1 = 0x000000F4
An example of writing to both MMRs follows.
divided by 8 clock source.
ADuC7033