ADUC7033BSTZ-88-RL Analog Devices Inc, ADUC7033BSTZ-88-RL Datasheet - Page 7

• Manufacturer Part Number: ADUC7033BSTZ-88-RL
• Description: Flash 96k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BSTZ-88-RL

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Parameter
MCU START-UP TIME
LIN INPUT/OUTPUT GENERAL
LIN VERSION 2.0 SPECIFICATION
Symmetry of Transmit
Symmetry of Receive Propagation
At Power-On
After Reset Event
From MCU Power-Down
Internal PLL Lock Time
Baud Rate
VDD
Input Capacitance
Input Leakage Current
LIN Comparator Response Time
I
I
I
I
I
V
V
V
V
V
V
V
V
GND Shift
R
V
Receive Propagation Delay
D1
LIN DOM MAX
LIN_PAS_REC
LIN
LIN_PAS_DOM
LIN_NO_GND
LIN_DOM
LIN_REC
LIN_CNT
HYS
LIN_DOM_DRV_LOSUP
LIN_DOM_DRV_HISUP
LIN_RECESSIVE
BAT
SLAVE
SERIAL DIODE
Oscillator Running
Crystal Powered Down
Propagation Delay
Delay
1
R
R
R
R
1
L
L
L
L
Shift
Wake Up from Interrupt
Wake Up from LIN
500 Ω
1000 Ω
500 Ω
1000 Ω
Wake Up from Interrupt
1
1
1
1
29
29
1
29
29
1
1
1
1
1
Test Conditions/Comments
Includes kernel power-on execution time
Includes kernel power-on execution time
Bus load conditions (CBUS||RBU): 1 nF||1 kΩ,
6.8 nF||660 Ω; 10 nF||500 Ω
Supply voltage range at which the LIN interface is
functional
Input (low) = IO_VSS
Using 22 Ω resistor
Current limit for driver when LIN bus is in
dominant state, V
Driver off, 7.0 V < V
VBAT disconnected, V
Input leakage V
Control unit disconnected from ground,
GND = V
LIN receiver dominant state, V
LIN receiver recessive state, V
LIN receiver center voltage, V
LIN receiver hysteresis voltage
LIN dominant output voltage, V
LIN dominant output voltage, V
LIN recessive output voltage
Slave termination resistance
Voltage drop at the Serial Diode D
V
V
V
Bus load conditions (CBUS||RBUS): 1 nF||1 kΩ,
6.8 nF||660 Ω; 10 nF||500 Ω
Duty Cycle 1,
TH
TH
V
D1 = t
DD (MIN)
DD (MIN)
DD (MIN)
SUP
REC(MAX)
DOM(MAX)
= 7.0 V . . . 18 V, t
BUS_REC(MIN)
= 7 V
= 7 V
= 7 V
DD
= 0.744 × V
= 0.581 × V
, 0 V < V
/
LIN
(
2 × t
BAT
= 0 V
LIN
LIN
= V
BAT
BIT
< 18 V, V
BIT
< 18 V, V
BAT
DD
)
,
= 50 μs,
Rev. B | Page 7 of 140
BAT (MAX)
,
= 0 V, 0 < V
DD
BAT
DD
DD
DD
DD
> 7.0 V
> 7.0 V
DD
= 12 V
= V
= 7 V
> 7.0 V
= 18 V
Ser_Int
LIN
LIN
< 18 V
− 0.7 V
Min
7
−800
40
−1
−1
0.6 V
0.475 V
0.6
0.8
0.8 V
0
0
0.4
−2
−2
0.396
1000
−20
20
DD
DD
DD
Typ
25
5
2
2
500
1
5.5
38
0.5 V
30
0.7
DD
Max
20,000
18
−400
90
200
+20
10
+1
0.4 V
0.525 V
0.175 V
1.2
2
0.1 V
0.1 V
47
1
+2
6
+2
DD
DD
DD
DD
DD
ADuC7033
Unit
ms
ms
ms
ms
ms
ms
Bits/sec
V
pF
μA
μs
mA
μA
μA
mA
mA
V
V
V
V
V
V
V
V
V
V
V
kΩ
V
μs
μs
μs