ADUC7126BSTZ126-RL Analog Devices Inc, ADUC7126BSTZ126-RL Datasheet - Page 68

• Manufacturer Part Number: ADUC7126BSTZ126-RL
• Description: ARM7 With 12-Bit ADC & DACs, 128kB Flash
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7126BSTZ126-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 41.78MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Size: 126KB (126K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x12b, D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7124/ADuC7126
SPIRX Register
Name:
Address:
Default Value:
Access:
Function:
SPITX Register
Name:
Address:
Default Value:
Access:
Function:
Table 101. SPICON MMR Bit Descriptions
Bit
[15:14]
13
12
11
10
Name
SPIMDE
SPITFLH
SPIRFLH
SPICONT
SPILP
SPITX
0xFFFF0A08
0x00
Write only
This 8-bit MMR is the SPI transmit register.
SPIRX
0xFFFF0A04
0x00
Read only
This 8-bit MMR is the SPI receive register.
Description
SPI IRQ mode bits. These bits configure when the Tx/Rx interrupts occur in a transfer.
[00] = Tx interrupt occurs when one byte has been transferred. Rx interrupt occurs when one or more bytes have
been received into the FIFO.
[01] = Tx interrupt occurs when two bytes have been transferred. Rx interrupt occurs when two or more bytes have
been received into the FIFO.
[10] = Tx interrupt occurs when three bytes have been transferred. Rx interrupt occurs when three or more bytes
have been received into the FIFO.
[11] = Tx interrupt occurs when four bytes have been transferred. Rx interrupt occurs when the Rx FIFO is full or four
bytes are present.
SPI Tx FIFO flush enable bit.
Set this bit to flush the Tx FIFO. This bit does not clear itself and should be toggled if a single flush is required.
If this bit is left high, then either the last transmitted value or 0x00 is transmitted, depending on the SPIZEN bit.
Any writes to the Tx FIFO are ignored while this bit is set.
Clear this bit to disable Tx FIFO flushing.
SPI Rx FIFO flush enable bit.
Set this bit to flush the Rx FIFO. This bit does not clear itself and should be toggled if a single flush is required.
If this bit is set incoming, data is ignored and no interrupts are generated.
If set and SPITMDE = 0, a read of the Rx FIFO initiates a transfer.
Clear this bit to disable Rx FIFO flushing.
Continuous transfer enable.
Set by the user to enable continuous transfer. In master mode, the transfer continues until no valid data is available
in the SPITX register. CS is asserted and remains asserted for the duration of each 8-bit serial transfer until SPITX is
empty.
Cleared by the user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer.
If valid data exists in the SPITX register, then a new transfer is initiated after a stall period of one serial clock cycle.
Loopback enable bit.
Set by the user to connect MISO to MOSI and test software.
Cleared by the user to be in normal mode.
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SPIDIV Register
Name:
Address:
Default Value:
Access:
Function:
SPICON Register
Name:
Address:
Default Value:
Access:
Function:
SPIDIV
0xFFFF0A0C
0x00
Read/write
This 8-bit MMR is the SPI baud rate selection
register.
SPICON
0xFFFF0A10
0x0000
Read/write
This 16-bit MMR configures the SPI
peripheral in both master and slave modes.