ADUC814BRU Analog Devices Inc, ADUC814BRU Datasheet - Page 64

• Manufacturer Part Number: ADUC814BRU
• Description: A/D Converter (A-D) IC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC814BRU

• Peak Reflow Compatible (260 C): No
• No. Of Bits: 12 Bit
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• No. Of Inputs: 6
• Features: +3V Or +5V Operation
• Package / Case: 28-TSSOP
• Rohs Status: RoHS non-compliant
• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 16.78MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 640 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: EVAL-ADUC814QSZ - KIT DEV FOR ADUC814 MICROCONVRTR
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ADuC814
TIMING SPECIFICATIONS
Table 34. Clock Input (External Clock Driven XTAL1)
AV
Parameter
t
t
t
t
t
1/t
t
t
1
2
3
4
5
6
CK
CKL
CKH
CKR
CKF
CORE
CYC
Logic 0 as shown in Figure 61.
loaded V
The core can operate at this frequency or at a binary submultiple called Core_Clk, selected via the PLLCON SFR.
AC inputs during testing are driven at DV
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the
C
ADuC814 internal PLL locks onto a multiple (512 times) the external crystal frequency of 32.768 kHz to provide a stable 16.777216 MHz internal clock for the system.
This number is measured at the default Core_Clk operating frequency of 2.09 MHz.
ADuC814 Machine Cycle Time is nominally defined as 12/Core_CLK.
LOAD
CORE
DD
for all outputs = 80 pF, unless otherwise noted.
= 2.7 V to 3.3 V or 4.75 V to 5.25 V, DV
OH
/V
OL
level occurs as shown in Figure 61.
XTAL1 Period
XTAL1 Width Low
XTAL1 Width High
XTAL1 Rise Time
XTAL1 Fall Time
ADuC814 Core Clock Frequency
ADuC814 Core Clock Period
ADuC814 Machine Cycle Time
DV
DD
– 0.5V
0.45V
DD
– 0.5 V for a Logic 1, and at 0.45 V for a Logic 0. Timing measurements are made at V
0. 2DV
0. 2DV
TEST POI NTS
1,2,3
DD
5
DD
6
– 0. 1V
+ 0. 9V
DD
t
4
CKH
= 2.7 V to 3.3 V or 4.75 V to 5.25 V; all specifications T
Figure 61. Timing Waveform Characteristics
Figure 60. XTAL1 Input
Rev. A | Page 64 of 72
V
t
LOAD
CKL
V
V
LOAD
LOAD
Min
0.131
0.72
– 0.1V
+ 0.1V
t
CKR
t
CK
32.768 kHz External Crystal
REFERENCE
T I MI NG
POI NT
30.52
15.16
15.16
20
Typ
20
0.476
5.7
t
CKF
MIN
V
V
LOAD
LOAD
to T
IH
min for a Logic 1, and at V
– 0.1V
+ 0.1V
MAX
Max
16.78
91.55
, unless otherwise noted
V
LOAD
Unit
µs
µs
µs
ns
ns
MHz
µs
µs
IL
max for a