CS4244-CNZ Cirrus Logic Inc, CS4244-CNZ Datasheet - Page 43

• Manufacturer Part Number: CS4244-CNZ
• Description: IC 4 Input / 5 Output CODEC
• Manufacturer: Cirrus Logic Inc

DS900PP2
4.8
Note:
4.8.1
Error Reporting and Interrupt Behavior
The CS4244 is equipped with a suite of error reporting and protection. The types of errors that are detected,
the notification method for these errors, and the steps needed to clear the errors are detailed in
It is important to note that the interrupt notification bits for all of the errors are triggered on the edge of the
occurrence of the event. They are not level-triggered and therefore do not indicate the presence of an error
in real time. This means that, a “1” in the error’s respective field inside the Interrupt Notification register only
indicates that the error has occurred since the last time the register was cleared and not necessarily that
the error is currently occurring.
Disallowed Test Mode Entry
(Note 36)
Serial Port Error
Clocking Error
ADCx Overflow
DACx Clip
36. This error is provided to aid in trouble shooting during software development. Entry into the test mode
Interrupt Masking
An occurrence of any of the errors mentioned above will cause the interrupt line to engage in order to no-
tify the system controller that an error has occurred. If it is preferred that the error not cause the interrupt
line to engage, this error can be masked in its respective mask register. It is important to note that, in the
event of an error, the interrupt notification bit for the respective error will reflect the occurrence of the
event, regardless of the setting of the mask bit. Setting the mask bit only prevents the interrupt pin from
being flagged upon the occurrence.
Name of Error
of the device may cause permanent damage to the device and should not be done intentionally.
Table 8. Error Reporting and Interrupt Behavior Details
the permitted full scale signal.
than the available rail voltage.
device is receiving is different
the
or the PLL is unlocked from
The speed mode which the
than the speed mode set in
ADC inputs are larger than
mode due to an errant I²C
DAC output level is larger
Device has entered test
FS/LRCK, or SCLK has
SPEED MODE[1:0]
Caused the Error
become invalid.
Event(s) that
input signal.
write.
bits,
Upon Occurrence?
Outputs Muted
Yes
Yes
No
No
No
(Normal operation will con-
tinue but audible distortion
Normal operation will con-
tinue but audible distortion
All PDNx bits must be
set and then cleared
to resume normal
operation?
will occur.)
will occur.
Yes
Yes
No
No
No
CS4244
Table
8.
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