CY7C1471V33-133AXC Cypress Semiconductor Corp, CY7C1471V33-133AXC Datasheet - Page 11

• Manufacturer Part Number: CY7C1471V33-133AXC
• Description: SRAM (Static RAM)
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1471V33-133AXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 72M (2M x 36)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Density: 72Mb
• Access Time (max): 6.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 21b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 4
• Supply Current: 305mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 2M
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2167; CY7C1471V33-133AXC

Pin Definitions
Functional Overview
The CY7C1471V33, CY7C1473V33, and CY7C1475V33 are
synchronous flow through burst SRAMs designed specifically to
eliminate
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with the
clock enable input signal (CEN). If CEN is HIGH, the clock signal
is not recognized and all internal states are maintained. All
synchronous operations are qualified with CEN. Maximum
access delay from the clock rise (t
device).
Accesses can be initiated by asserting all three chip enables
(CE
is active LOW and ADV/LD is asserted LOW, the address
presented to the device is latched. The access can either be a
read or write operation, depending on the status of the write
enable (WE). Byte write select (BW
byte write operations.
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self timed write circuitry.
Three synchronous chip enables (CE
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
must be driven LOW after the device is deselected to load a new
address for the next operation.
Single Read Accesses
A read access is initiated when these conditions are satisfied at
clock rise:
■
■
■
■
The address presented to the address inputs is latched into the
address register and presented to the memory array and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the
Document Number: 38-05288 Rev. *L
Name
TDO
TDI
TMS
TCK
NC
CEN is asserted LOW
CE
WE is deasserted HIGH
ADV/LD is asserted LOW.
1
, CE
1
, CE
2
, CE
2
wait
, and CE
3
) active at the rising edge of the clock. If (CEN)
states
JTAG serial input
JTAG serial input
3
synchronous
synchronous
synchronous
(continued)
JTAG serial
are all asserted active
output
-clock
JTAG
during
IO
-
write-read
X
CDV
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
JTAG feature is not used, this pin must be left unconnected. This pin is not available on
TQFP packages.
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
is not used, this pin can be left floating or connected to V
pin is not available on TQFP packages.
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
is not used, this pin can be disconnected or connected to V
TQFP packages.
Clock input to the JTAG circuitry. If the JTAG feature is not used, this pin must be
connected to V
No connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address
expansion pins and are not internally connected to the die.
) can be used to conduct
1
) is 6.5 ns (133-MHz
, CE
2
transitions.
, CE
SS
3
) and an
. This pin is not available on TQFP packages.
All
output buffers. The data is available within 6.5 ns (133-MHz
device) provided OE is active LOW. After the first clock of the
read access, the output buffers are controlled by OE and the
internal control logic. OE must be driven LOW to drive out the
requested data. On the subsequent clock, another operation
(read/write/deselect) can be initiated. When the SRAM is
deselected at clock rise by one of the chip enable signals, output
is be tri-stated immediately.
Burst Read Accesses
The CY7C1471V33, CY7C1473V33 and CY7C1475V33 have
an on-chip burst counter that enables the user to supply a single
address and conduct up to four reads without reasserting the
address inputs. ADV/LD must be driven LOW to load a new
address into the SRAM, as described in the
Accesses
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved burst
sequence. Both burst counters use A0 and A1 in the burst
sequence, and wraps around when incremented sufficiently. A
HIGH input on ADV/LD increments the internal burst counter
regardless of the state of chip enable inputs or WE. WE is latched
at the beginning of a burst cycle. Therefore, the type of access
(read or write) is maintained throughout the burst sequence.
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
and CE
The address presented to the address bus is loaded into the
Address Register. The Write signals are latched into the Control
Logic block. The data lines are automatically tri-stated
regardless of the state of the OE input signal. This allows the
external logic to present the data on DQs and DQP
On the next clock rise the data presented to DQs and DQP
a subset for Byte Write operations, see
Read/Write” on page 14
device and the write is complete. Additional accesses
(read/write/deselect) can be initiated on this cycle.
The data written during the write operation is controlled by BW
signals.
Description
3
are all asserted active, and (3) WE is asserted LOW.
section. The sequence of the burst counter is
The
CY7C1471V33,
DD
for details) inputs is latched into the
DD
through a pull up resistor. This
. This pin is not available on
CY7C1471V33
CY7C1473V33
CY7C1475V33
CY7C1473V33,
“Truth Table for
Page 11 of 36
Single Read
X
.
1
, CE
X
and
(or
2
X
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