CY7C1471V33-133AXC Cypress Semiconductor Corp, CY7C1471V33-133AXC Datasheet - Page 25

• Manufacturer Part Number: CY7C1471V33-133AXC
• Description: SRAM (Static RAM)
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1471V33-133AXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 72M (2M x 36)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Density: 72Mb
• Access Time (max): 6.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 21b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 4
• Supply Current: 305mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 2M
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2167; CY7C1471V33-133AXC

Switching Characteristics
Over the Operating Range. Unless otherwise noted in the following table, timing reference level is 1.5 V when V
1.25 V when V
Notes
Document Number: 38-05288 Rev. *L
t
Clock
t
t
t
Output Times
t
t
t
t
t
t
t
Setup Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
18. This part has an internal voltage regulator; t
19. t
20. At any supplied voltage and temperature, t
21. This parameter is sampled and not 100% tested.
POWER
CYC
CH
CL
CDV
DOH
CLZ
CHZ
OEV
OELZ
OEHZ
AS
ALS
WES
CENS
DS
CES
AH
ALH
WEH
CENH
DH
CEH
Parameter
can be initiated.
from steady-state voltage.
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve high Z before low Z under the same system conditions.
CHZ
, t
CLZ
[18]
,t
OELZ
DDQ
, and t
= 2.5 V. Test conditions shown in (a) of
OEHZ
are specified with AC test conditions shown in part (b)
Clock cycle time
Clock HIGH
Clock LOW
Data output valid after CLK rise
Data output hold after CLK rise
Clock to low Z
Clock to high Z
OE LOW to output valid
OE LOW to output low Z
OE HIGH to output high Z
Address setup before CLK rise
ADV/LD setup before CLK rise
WE, BW
CEN setup before CLK rise
Data input setup before CLK rise
Chip enable setup before CLK rise
Address hold after CLK rise
ADV/LD hold after CLK rise
WE, BW
CEN hold after CLK rise
Data input hold after CLK rise
Chip enable hold after CLK rise
OEHZ
X
X
POWER
setup before CLK rise
hold after CLK rise
is less than t
is the time that the power needs to be supplied above V
[19, 20, 21]
[19, 20, 21]
Description
OELZ
[19, 20, 21]
and t
[19, 20, 21]
CHZ
“AC Test Loads and Waveforms” on page 24
is less than t
of“AC Test Loads and Waveforms” on page
CLZ
to eliminate bus contention between SRAMs when sharing the same
Min
7.5
2.5
2.5
2.5
3.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
–
–
–
0
–
133 MHz
DD
(minimum) initially, before a read or write operation
Max
6.5
3.8
3.0
3.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
24. Transition is measured ±200 mV
Min
3.0
3.0
2.5
3.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
10
1
–
–
–
0
–
117 MHz
unless otherwise noted.
CY7C1471V33
CY7C1473V33
CY7C1475V33
Max
8.5
4.5
3.8
4.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
DDQ
= 3.3 V and is
Page 25 of 36
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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