DSPIC33EP256MU810-I/PF Microchip Technology, DSPIC33EP256MU810-I/PF Datasheet - Page 150

• Manufacturer Part Number: DSPIC33EP256MU810-I/PF
• Description: 100 PINS, 256KB Flash, 28KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 14x14x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP256MU810-I/PF

• Processor Series: DSPIC33E
• Core: dsPIC
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 256KB (85.5K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 12K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Details

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
8.1
Each DMAC Channel x (where x = 0 through 14)
contains the following registers:
• 16-bit DMA Channel Control register (DMAxCON)
• 16-bit DMA Channel IRQ Select register
• 32-bit DMA RAM Primary Start Address register
• 32-bit DMA RAM Secondary Start Address
• 16-bit DMA Peripheral Address register (DMAxPAD)
• 14-bit DMA Transfer Count register (DMAxCNT)
REGISTER 8-1:
DS70616E-page 150
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10-6
bit 5-4
bit 3-2
bit 1-0
(DMAxREQ)
(DMAxSTA)
register (DMAxSTB)
R/W-0
CHEN
U-0
—
DMAC Registers
CHEN: Channel Enable bit
1 = Channel enabled
0 = Channel disabled
SIZE: Data Transfer Size bit
1 = Byte
0 = Word
DIR: Transfer Direction bit (source/destination bus select)
1 = Read from DPSRAM (or RAM) address, write to peripheral address
0 = Read from Peripheral address, write to DPSRAM (or RAM) address
HALF: Block Transfer Interrupt Select bit
1 = Initiate interrupt when half of the data has been moved
0 = Initiate interrupt when all of the data has been moved
NULLW: Null Data Peripheral Write Mode Select bit
1 = Null data write to peripheral in addition to DPSRAM (or RAM) write (DIR bit must also be clear)
0 = Normal operation
Unimplemented: Read as
AMODE<1:0>: DMA Channel Addressing Mode Select bits
11 = Reserved
10 = Peripheral Indirect Addressing mode
01 = Register Indirect without Post-Increment mode
00 = Register Indirect with Post-Increment mode
Unimplemented: Read as
MODE<1:0>: DMA Channel Operating Mode Select bits
11 = One-Shot, Ping-Pong modes enabled (one block transfer from/to each DMA buffer)
10 = Continuous, Ping-Pong modes enabled
01 = One-Shot, Ping-Pong modes disabled
00 = Continuous, Ping-Pong modes disabled
R/W-0
SIZE
U-0
—
DMA
X
CON: DMA CHANNEL
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
DIR
AMODE<1:0>
‘
‘
0
0
’
’
R/W-0
R/W-0
HALF
Preliminary
X
CONTROL REGISTER
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
NULLW
R/W-0
Additional status registers (DMAPWC, DMARQC,
DMAPPS, DMALCA, and DSADR) are common to all
DMAC channels. These status registers provide infor-
mation on write and request collisions, as well as on
last address and channel access information.
The interrupt flags (DMAxIF) are located in an IFSx
register in the interrupt controller. The corresponding
interrupt enable control bits (DMAxIE) are located in
an IECx register in the interrupt controller, and the
corresponding interrupt priority control bits (DMAxIP)
are located in an IPCx register in the interrupt
controller.
U-0
—
U-0
U-0
—
—
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x = Bit is unknown
R/W-0
U-0
—
MODE<1:0>
R/W-0
U-0
—
bit 8
bit 0