DSPIC33EP256MU810-I/PF Microchip Technology, DSPIC33EP256MU810-I/PF Datasheet - Page 432

• Manufacturer Part Number: DSPIC33EP256MU810-I/PF
• Description: 100 PINS, 256KB Flash, 28KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 14x14x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP256MU810-I/PF

• Processor Series: DSPIC33E
• Core: dsPIC
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 256KB (85.5K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 12K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Details

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
REGISTER 28-2:
DS70616E-page 432
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at Reset
bit 15
bit 14-13
bit 12-11
bit 10
bit 9-8
bit 7-6
bit 5-2
bit 1-0
Note 1:
R/W-0
BUSY
R-0
WAITB<1:0>
2:
3:
The applied Wait state depends on whether data and address are multiplexed or demultiplexed. See
28.4.1.8 “Wait States” in Section 28. “Parallel Master Port (PMP)” (DS70576) in the “dsPIC33E/
PIC24E Family Reference Manual” for more information.
WAITB<1:0> and WAITE<1:0> bits are ignored whenever WAITM<3:0> = 0000.
T
P
= 1/F
BUSY: Busy bit (Master mode only)
1 = Port is busy
0 = Port is not busy
IRQM<1:0>: Interrupt Request Mode bits
11 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode),
10 = Reserved
01 = Interrupt generated at the end of the read/write cycle
00 = No Interrupt generated
INCM<1:0>: Increment Mode bits
11 = PSP read and write buffers auto-increment (Legacy PSP mode only)
10 = Decrement ADDR by 1 every read/write cycle
01 = Increment ADDR by 1 every read/write cycle
00 = No increment or decrement of address
MODE16: 8/16-bit Mode bit
1 = 16-bit mode: data register is 16 bits, a read/write to the data register invokes two 8-bit transfers
0 = 8-bit mode: data register is 8 bits, a read/write to the data register invokes one 8-bit transfer
MODE<1:0>: Parallel Port Mode Select bits
11 = Master Mode 1 (PMCSx, PMRD/PMWR, PMENB, PMBE, PMA<x:0>, and PMD<7:0>)
10 = Master Mode 2 (PMCSx, PMRD, PMWR, PMBE, PMA<x:0>, and PMD<7:0>)
01 = Enhanced PSP, control signals (PMRD, PMWR, PMCSx, PMD<7:0>, and PMA<1:0>)
00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCSx, and PMD<7:0>)
WAITB<1:0>: Data Setup to Read/Write/Address Phase Wait State Configuration bits
11 = Data wait of 4 T
10 = Data wait of 3 T
01 = Data wait of 2 T
00 = Data wait of 1 T
WAITM<3:0>: Read to Byte Enable Strobe Wait State Configuration bits
1111 = Wait of additional 15 T
•
•
•
0001 = Wait of additional 1 T
0000 = No additional Wait cycles (operation forced into one T
WAITE<1:0>: Data Hold After Strobe Wait State Configuration bits
11 = Wait of 4 T
10 = Wait of 3 T
01 = Wait of 2 T
00 = Wait of 1 T
(1,2,3)
R/W-0
R/W-0
P
or on a read/write operation when PMA<1:0> = 11 (Addressable PSP mode only)
.
PMMODE: PARALLEL MASTER PORT MODE REGISTER
IRQM<1:0>
W = Writable bit
‘1’ = Bit is set
P
P
P
P
R/W-0
R/W-0
P
P
P
P
(demultiplexed/multiplexed); address phase of 4 T
(demultiplexed/multiplexed); address phase of 3 T
(demultiplexed/multiplexed); address phase of 2 T
(demultiplexed/multiplexed); address phase of 1 T
P
P
R/W-0
R/W-0
Preliminary
WAITM<3:0>
INCM<1:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
R/W-0
MODE16
P
R/W-0
R/W-0
)
(1,2,3)
 2009-2011 Microchip Technology Inc.
P
P
P
P
x = Bit is unknown
(multiplexed)
(multiplexed)
(multiplexed)
(multiplexed)
R/W-0
R/W-0
WAITE<1:0>
MODE<1:0>
(1,2,3)
(1,2,3)
R/W-0
R/W-0
bit 8
bit 0