DSPIC33EP256MU810-I/PF Microchip Technology, DSPIC33EP256MU810-I/PF Datasheet - Page 196

• Manufacturer Part Number: DSPIC33EP256MU810-I/PF
• Description: 100 PINS, 256KB Flash, 28KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 14x14x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP256MU810-I/PF

• Processor Series: DSPIC33E
• Core: dsPIC
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 256KB (85.5K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 12K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Details

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
11.4.3.2
In contrast to inputs, the outputs of the peripheral pin
select options are mapped on the basis of the pin. In
this case, a control register associated with a particular
pin dictates the peripheral output to be mapped. The
RPORx registers are used to control output mapping.
Like the RPINRx registers, each register contains sets
of 6 bit fields, with each set associated with one RPn
pin (see
value of the bit field corresponds to one of the periph-
erals, and that peripheral’s output is mapped to the pin
(see
A null output is associated with the output register reset
value of ‘0’. This is done to ensure that remappable out-
puts remain disconnected from all output pins by
default.
TABLE 11-3:
DS70616E-page 196
DEFAULT PORT
U1TX
U1RTS
U2TX
U2RTS
SDO1
SCK1
SS1
SS2
CSDO
CSCK
COFS
C1TX
C2TX
OC1
OC2
OC3
OC4
OC5
OC6
OC7
OC8
C1OUT
C2OUT
C3OUT
U3TX
U3RTS
Note 1:
Table 11-3
Function
Register 11-44
This function is available in dsPIC33EPXXXMU806/810/814 devices only.
Output Mapping
and
OUTPUT SELECTION FOR REMAPPABLE PINS (RPn)
Figure
through
11-3).
Register
RPnR<5:0>
000000
000001
000010
000011
000100
000101
000110
000111
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
11-51). The
Preliminary
RPn tied to default pin
RPn tied to UART1 transmit
RPn tied to UART1 ready to send
RPn tied to UART2 transmit
RPn tied to UART2 ready to send
RPn tied to SPI1 data output
RPn tied to SPI1 clock output
RPn tied to SPI1 slave select
RPn tied to SPI2 slave select
RPn tied to DCI data output
RPn tied to DCI clock output
RPn tied to DCI FSYNC output
RPn tied to CAN1 transmit
RPn tied to CAN2 transmit
RPn tied to Output Compare 1 output
RPn tied to Output Compare 2 output
RPn tied to Output Compare 3 output
RPn tied to Output Compare 4 output
RPn tied to Output Compare 5 output
RPn tied to Output Compare 6 output
RPn tied to Output Compare 7 output
RPn tied to Output Compare 8 output
RPn tied to Comparator Output 1
RPn tied to Comparator Output 2
RPn tied to Comparator Output 3
RPn tied to UART3 transmit
RPn tied to UART3 ready to send
FIGURE 11-3:
QEI2CCMP Output
REFCLK Output
U1RTS Output
U1TX Output
Output Name
Default
 2009-2011 Microchip Technology Inc.
RPnR<5:0>
MULTIPLEXING OF
REMAPPABLE OUTPUT
FOR RPn
48
49
0
1
2
Output Data
RPn