DSPIC33EP256MU810-I/PF Microchip Technology, DSPIC33EP256MU810-I/PF Datasheet - Page 275

• Manufacturer Part Number: DSPIC33EP256MU810-I/PF
• Description: 100 PINS, 256KB Flash, 28KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 14x14x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP256MU810-I/PF

• Processor Series: DSPIC33E
• Core: dsPIC
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 256KB (85.5K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 12K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Details

REGISTER 16-6:
REGISTER 16-7:
 2009-2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-3
bit 2-0
Note 1:
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
R/W-1
R/W-1
dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
U-0
U-0
—
—
These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
Unimplemented: Read as ‘0’
PCLKDIV<2:0>: PWM Input Clock Prescaler (Divider) Select bits
111 = Reserved
110 = Divide by 64, maximum PWM timing resolution
101 = Divide by 32, maximum PWM timing resolution
100 = Divide by 16, maximum PWM timing resolution
011 = Divide by 8, maximum PWM timing resolution
010 = Divide by 4, maximum PWM timing resolution
001 = Divide by 2, maximum PWM timing resolution
000 = Divide by 1, maximum PWM timing resolution (power-on default)
STPER<15:0>: Secondary Master Time Base (PMTMR) Period Value bits
R/W-1
R/W-1
U-0
U-0
—
—
STCON2: PWM SECONDARY CLOCK DIVIDER SELECT REGISTER
STPER: SECONDARY MASTER TIME BASE PERIOD REGISTER
W = Writable bit
W = Writable bit
‘1’ = Bit is set
‘1’ = Bit is set
R/W-1
R/W-1
U-0
U-0
—
—
R/W-1
R/W-1
U-0
U-0
Preliminary
—
—
STPER<15:8>
STPER<7:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-1
R/W-1
U-0
U-0
—
—
R/W-0
R/W-1
R/W-0
U-0
—
(1)
PCLKDIV<2:0>
x = Bit is unknown
x = Bit is unknown
R/W-0
R/W-1
R/W-0
U-0
—
(1)
DS70616E-page 275
(1)
R/W-0
R/W-1
R/W-0
U-0
—
bit 8
bit 0
bit 8
bit 0