KSZ8851-16MLLI Micrel Inc, KSZ8851-16MLLI Datasheet - Page 48

• Manufacturer Part Number: KSZ8851-16MLLI
• Description: 10/100BT Ethernet MAC + PHY With Generic (8, 16-bit) Bus Interface (I-Temp)
• Manufacturer: Micrel Inc

Specifications of KSZ8851-16MLLI

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Bus
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-3505

Transmit Status Register (0x72 – 0x73): TXSR
This register keeps the status of the last transmitted frame.
Receive Control Register 1 (0x74 – 0x75): RXCR1
This register holds control information programmed by the CPU to control the receive function.
August 2009
Micrel, Inc.
Bit
6
5
4
3
2
1
0
Bit
15-14
13
12
11-6
5-0
Bit
15
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
-
-
0x0
Default Value
Default Value
0x0
Default Value
R/W
RW
RW
RW
RW
RW
RW
RW
R/W
RO
RO
RO
RO
RO
R/W
RW
Description
TCGTCP Transmit Checksum Generation for TCP
When this bit is set, The KSZ8851-16MLL is enabled to transmit TCP frame checksum
generation.
TCGIP Transmit Checksum Generation for IP
When this bit is set, The KSZ8851-16MLL is enabled to transmit IP header checksum
generation.
FTXQ Flush Transmit Queue
When this bit is set, The transmit queue memory is cleared and TX frame pointer is
reset.
Note: Disable the TXE transmit enable bit[0] first before set this bit, then clear this bit
to normal operation.
TXFCE Transmit Flow Control Enable
When this bit is set and the KSZ8851-16MLL is in full-duplex mode, flow control is
enabled. The KSZ8851-16MLL transmits a PAUSE frame when the Receive Buffer
capacity reaches a threshold level that will cause the buffer to overflow.
When this bit is set and the KSZ8851-16MLL is in half-duplex mode, back-pressure
flow control is enabled. When this bit is cleared, no transmit flow control is enabled.
TXPE Transmit Padding Enable
When this bit is set, the KSZ8851-16MLL automatically adds a padding field to a
packet shorter than 64 bytes.
Note: Setting this bit requires enabling the add CRC feature (bit1=1) to avoid CRC
errors for the transmit packet.
TXCE Transmit CRC Enable
When this bit is set, the KSZ8851-16MLL automatically adds a 32-bit CRC checksum
field to the end of a transmit frame.
TXE Transmit Enable
When this bit is set, the transmit module is enabled and placed in a running state.
When reset, the transmit process is placed in the stopped state after the transmission
of the current frame is completed.
Description
Reserved.
TXLC Transmit Late Collision
This bit is set when a transmit Late Collision occurs.
TXMC Transmit Maximum Collision
This bit is set when a transmit Maximum Collision is reached.
Reserved.
TXFID Transmit Frame ID
This field identifies the transmitted frame. All of the transmit status information in this
register belongs to the frame with this ID.
Description
FRXQ Flush Receive Queue
When this bit is set, The receive queue memory is cleared and RX frame pointer is reset.
Note: Disable the RXE receive enable bit[0] first before set this bit, then clear this bit to
normal operation.
48
KSZ8851-16MLL/MLLI
M9999-083109-2.0