KSZ8851-16MLLI Micrel Inc, KSZ8851-16MLLI Datasheet - Page 57

• Manufacturer Part Number: KSZ8851-16MLLI
• Description: 10/100BT Ethernet MAC + PHY With Generic (8, 16-bit) Bus Interface (I-Temp)
• Manufacturer: Micrel Inc

Specifications of KSZ8851-16MLLI

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Bus
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-3505

TX Next Total Frames Size Register (0x9E – 0x9F): TXNTFSR
This register is used by the host CPU to program the total amount of TXQ buffer space requested for the next transmit.
MAC Address Hash Table Register 0 (0xA0 – 0xA1): MAHTR0
The 64-bit MAC address table is used for group address filtering and it is enabled by selecting item 5 “Hash perfect” mode
in Table 3 (Address Filtering Scheme). This value is defined as the six most significant bits from CRC circuit calculation
result that is based on 48-bit of DA input. The two most significant bits select one of the four registers to be used, while
the others determine which bit within the register.
Multicast table register 0.
MAC Address Hash Table Register 1 (0xA2 – 0xA3): MAHTR1
Multicast table register 1.
MAC Address Hash Table Register 2 (0xA4 – 0xA5): MAHTR2
Multicast table register 2.
MAC Address Hash Table Register 3 (0xA6 – 0xA7): MAHTR3
Multicast table register 3.
August 2009
Micrel, Inc.
7-0
Bit
15-0
Bit
15-0
Bit
15-0
Bit
15-0
0x00
Default Value
0x0000
Default Value
0x0
Default Value
0x0
Default Value
0x0
RW
R/W
RW
R/W
RW
R/W
RW
R/W
RW
RXFCT Receive Frame Count Threshold
To program received frame count threshold value.
When bit 5 set to 1 in RXQCR register, the KSZ8851-16MLL will set RX interrupt (bit 13 in
ISR) when the number of received frames in RXQ buffer exceeds the threshold set in this
register.
Description
TXNTFS TX Next Total Frames Size
The host CPU is used to program the total amount of TXQ buffer space which is required
for next total transmit frames size in double-word count.
When bit 1 (TXQ memory available monitor) is set to 1 in TXQCR register, the KSZ8851-
16MLL will generate interrupt (bit 6 in ISR register) to CPU when TXQ memory is available
based upon the total amount of TXQ space requested by CPU at this register.
Description
HT0 Hash Table 0
When the appropriate bit is set, if the packet received with DA matches the CRC, the
hashing function is received without being filtered.
When the appropriate bit is cleared, the packet will drop.
Description
HT1 Hash Table 1
When the appropriate bit is set, if the packet received with DA matches the CRC, the
hashing function is received without being filtered.
When the appropriate bit is cleared, the packet will drop.
Note: When the receive all (RXAE) or receive multicast (RXME) bit is set in the RXCR1, all
multicast addresses are received regardless of the multicast table value.
Description
HT2 Hash Table 2
When the appropriate bit is set, if the packet received with DA matches the CRC, the
hashing function is received without being filtered.
When the appropriate bit is cleared, the packet will drop.
Note: When the receive all (RXAE) or receive multicast (RXME) bit is set in the RXCR1, all
multicast addresses are received regardless of the multicast table value.
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KSZ8851-16MLL/MLLI
M9999-083109-2.0