KSZ8851-16MLLI Micrel Inc, KSZ8851-16MLLI Datasheet - Page 56

• Manufacturer Part Number: KSZ8851-16MLLI
• Description: 10/100BT Ethernet MAC + PHY With Generic (8, 16-bit) Bus Interface (I-Temp)
• Manufacturer: Micrel Inc

Specifications of KSZ8851-16MLLI

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Bus
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-3505

0x94 – 0x9B: Reserved
RX Frame Count & Threshold Register (0x9C – 0x9D): RXFCTR
This register indicates the current total amount of received frame count in RXQ frame buffer and also is used to program
the received frame count threshold.
August 2009
Micrel, Inc.
Bit
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit
15-8
0x0
0x0
0x0
0x0
0x1
0x1
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Default Value
Default Value
0x00
R/W
RO
(W1C)
RO
RO
(W1C)
RO
RO
(W1C)
RO
(W1C)
RO
RO
(W1C)
RO
RO
RO
RO
RO
RO
R/W
RO
Description
MAC interface and the QMU TXQ is ready for new frames from the host.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
RXIS Receive Interrupt Status
When this bit is set, it indicates that the QMU RXQ has received at least a frame from the
MAC interface and the frame is ready for the host CPU to process.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
Reserved
RXOIS Receive Overrun Interrupt Status
When this bit is set, it indicates that the Receive Overrun status has occurred.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
Reserved
TXPSIS Transmit Process Stopped Interrupt Status
When this bit is set, it indicates that the Transmit Process has stopped.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
RXPSIS Receive Process Stopped Interrupt Status
When this bit is set, it indicates that the Receive Process has stopped.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
Reserved
TXSAIS Transmit Space Available Interrupt Status
When this bit is set, it indicates that Transmit memory space available status has occurred.
When this bit is reset, the Transmit memory space available interrupt is disabled.
RXWFDIS Receive Wakeup Frame Detect Interrupt Status
When this bit is set, it indicates that Receive wakeup frame detect status has occurred.
Write “1000” to PMECR[5:2] to clear this bit
RXMPDIS Receive Magic Packet Detect Interrupt Status
When this bit is set, it indicates that Receive magic packet detect status has occurred.
Write “0100” to PMECR[5:2] to clear this bit.
LDIS Linkup Detect Interrupt Status
When this bit is set, it indicates that wake-up from linkup detect status has occurred. Write
“0010” to PMECR[5:2] to clear this bit.
EDIS Energy Detect Interrupt Status
When this bit is set and bit 2=1, bit 0=0 in IER register, it indicates that wake-up from
energy detect status has occurred. When this bit is set and bit 2, 0=1 in IER register, it
indicates that wake-up from delay energy detect status has occurred.
Write “0001” to PMECR[5:2] to clear this bit.
Reserved.
Reserved
Description
RXFC RX Frame Count
To indicate the total received frames in RXQ frame buffer when receive interrupt (bit13=1 in
ISR) occurred and write “1” to clear this bit 13 in ISR. The host CPU can start to read the
updated receive frame header information in RXFHSR/RXFHBCR registers after read this
RX frame count register.
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KSZ8851-16MLL/MLLI
M9999-083109-2.0