KSZ8851-16MLLI Micrel Inc, KSZ8851-16MLLI Datasheet - Page 8

• Manufacturer Part Number: KSZ8851-16MLLI
• Description: 10/100BT Ethernet MAC + PHY With Generic (8, 16-bit) Bus Interface (I-Temp)
• Manufacturer: Micrel Inc

Specifications of KSZ8851-16MLLI

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Bus
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-3505

Micrel, Inc.
KSZ8851-16MLL/MLLI
List of Figures
Figure 1. KSZ8851-16MLL/MLLI Functional Diagram ............................................................................................................ 1
Figure 2. 48-Pin LQFP ......................................................................................................................................................... 10
Figure 3. Typical Straight Cable Connection ........................................................................................................................ 18
Figure 4. Typical Crossover Cable Connection .................................................................................................................... 19
Figure 5. Auto Negotiation and Parallel Operation ............................................................................................................... 20
Figure 6. KSZ8851-16MLL 8-Bit and 16-Bit Data Bus Connections..................................................................................... 24
Figure 7. Host TX Single Frame in Manual Enqueue Flow Diagram .................................................................................... 27
Figure 8. Host TX Multiple Frames in Auto- Enqueue Flow Diagram ................................................................................... 28
Figure 9. Host RX Single or Multiple Frames in Auto-Dequeue Flow Diagram .................................................................... 30
Figure 10. PHY Port 1 Near-end (Remote) and Host Far-end (Local) Loopback Paths....................................................... 32
Figure 11. Asynchronous Cycle ............................................................................................................................................ 72
Figure 12. Auto Negotiation Timing ...................................................................................................................................... 73
Figure 13. Reset Timing........................................................................................................................................................ 74
Figure 14. EEPROM Read Cycle Timing Diagram ............................................................................................................... 75
Figure 15. 48-Pin (7mm x 7mm) LQFP................................................................................................................................. 77
August 2009
8
M9999-083109-2.0