KSZ8995FQI Micrel Inc, KSZ8995FQI Datasheet - Page 14

• Manufacturer Part Number: KSZ8995FQI
• Description: 5 Port 10/100 Switch With PHY And Frame Buffers ( )
• Manufacturer: Micrel Inc

Specifications of KSZ8995FQI

• Number Of Primary Switch Ports: 5
• Internal Memory Buffer Size: 64
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Temperature Classification: Industrial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-3300

Semptember 2008
Notes:
1.
2.
Pin Number
P = Power supply.
I = Input.
O = Output.
I/O = Bidirectional.
Gnd = Ground.
Ipu = Input w/internal pull-up.
Ipd = Input w/internal pull-down.
Ipd/O = Input w/internal pull-down during reset, output pin otherwise.
Ipu/O = Input w/internal pull-up during reset, output pin otherwise.
NC = No connect.
PU = Strap pin pull-up.
PD = Strap pull-down.
Otri = Output tristated.
Fulld = Full duplex
82
83
84
85
86
87
88
89
90
91
Pin Name
SMRXD1
SMRXD0
SCONF1
SCONF0
LED5-2
LED5-1
GNDD
SCOL
SCRS
VDDC
Type
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipu/O
Ipu/O
Gnd
Ipd
Ipd
P
(1)
Port
5
5
Pin Function
Switch MII receive bit 1. Strap option: PD (default) = Switch MII in
100Mbps mode; PU = Switch MII in 10Mbps mode.
Switch MII receive bit 0; Strap option: LED mode
PD (default) = mode 0; PU = mode 1. See “Register 11.”
Mode 0, link at
100/Full LEDx[2,1,0]=0,0,0
10/Full LEDx[2,1,0]=0,0,1
Mode 1, link at
100/Full LEDx[2,1,0]=0,1,0
10/Full LEDx[2,1,0]=1,0,0
LEDX_2
LEDX_1
LEDX_0
Switch MII collision detect.
Switch mode carrier sense.
Dual MII configuration pin. For the Switch MII, KSZ8995MA supports
both MAC mode and PHY mode, KSZ8995FQ supports PHY mode
only.
Pin# (91, 86, 87):
000
001
010
011
100
101
110
111
Dual MII configuration pin.
Digital ground.
1.8V digital core V
LED indicator 2. Strap option: aging setup. See “Aging” section.
PU (default) = aging enable; PD = aging disable.
LED indicator 1. Strap option: PU (default): enable PHY[5] MII I/F. PD:
tristate all PHY[5] MII output. See “Pin 86 SCONF1.”
14
(2)
DD
.
Switch MII
Disable, Otri
PHY Mode MII
MAC Mode MII
PHY Mode SNI
Disable
PHY Mode MII
MAC Mode MII
PHY Mode SNI
Fulld/Col
Mode 0
Lnk/Act
Speed
100/Half LEDx[2,1,0]=0,1,0
10/Half LEDx[2,1,0]=0,1,1
100/Half LEDx[2,1,0]=0,1,1
10/Half LEDx[2,1,0]=1,0,1
PHY [5] MII
Disable, Otri
Disable, Otri
Disable, Otri
Disable, Otri
Disable
PHY Mode MII
PHY Mode MII
PHY Mode MII
100Lnk/Act
Full duplex
10Lnk/Act
Mode 1
M9999-091508