KSZ8995FQI Micrel Inc, KSZ8995FQI Datasheet - Page 76

• Manufacturer Part Number: KSZ8995FQI
• Description: 5 Port 10/100 Switch With PHY And Frame Buffers ( )
• Manufacturer: Micrel Inc

Specifications of KSZ8995FQI

• Number Of Primary Switch Ports: 5
• Internal Memory Buffer Size: 64
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Temperature Classification: Industrial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-3300

Semptember 2008
Reset Circuit Diagram
Micrel recommends the following discrete reset circuit as shown in Figure 22 when powering up the KS8895MA device.
For the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), we recommend
the reset circuit as shown in Figure 23.
At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the Micrel device. The reset out from
CPU/FPGA provides warm reset after power up. It is also recommended to power up the VDD core voltage earlier than
VDDIO voltage. At worst case, the both VDD core and VDDIO voltages should come up at the same time.
Figure 23. Recommended Circuit for Interfacing with CPU/FPGA Reset
KS8995MA
RST
Figure 22. Recommended Reset Circuit
KS8995MA
D1
D1: 1N4148
RST
10µF
VCC
C
76
D1
R
10k
D2
10µF
VCC
D1, D2: 1N4148
C
R
10k
RST_OUT_n
CPU/FPGA
M9999-091508