KSZ8995FQI Micrel Inc, KSZ8995FQI Datasheet - Page 50

• Manufacturer Part Number: KSZ8995FQI
• Description: 5 Port 10/100 Switch With PHY And Frame Buffers ( )
• Manufacturer: Micrel Inc

Specifications of KSZ8995FQI

• Number Of Primary Switch Ports: 5
• Internal Memory Buffer Size: 64
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Temperature Classification: Industrial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-3300

Semptember 2008
Note:
Bits 2-0 are used for spanning tree support. See “Spanning Tree Support” section.
Register 19 (0x13): Port 1 Control 3
Register 35 (0x23): Port 2 Control 3
Register 51 (0x33): Port 3 Control 3
Register 67 (0x43): Port 4 Control 3
Register 83 (0x53): Port 5 Control 3
Register 20 (0x14): Port 1 Control 4
Register 36 (0x24): Port 2 Control 4
Register 52 (0x34): Port 3 Control 4
Register 68 (0x44): Port 4 Control 4
Register 84 (0x54): Port 5 Control 4
Note:
Registers 19 and 20 (and those corresponding to other ports) serve two purposes: (1) Associated with the ingress untagged packets, and used for
egress tagging; (2) Default VID for the ingress untagged or null-VID-tagged packets, and used for address look up.
Address
3
2
1
0
Address
7-0
Address
7-0
Name
Default Tag [15:8]
Name
Default Tag [7:0]
Name
Back Pressure Enable
Transmit Enable
Receive Enable
Learning Disable
Description
Port’s default tag, containing:
7-5: user priority bits
4: CFI bit
3-0 : VID[11:8]
Description
Default port 1’s tag, containing:
7-0: VID[7:0]
Description
1, enable port half-duplex back pressure.
0, disable port half-duplex back pressure.
1, enable packet transmission on the port.
0, disable packet transmission on the port.
1, enable packet reception on the port.
0, disable packet reception on the port.
1, disable switch address learning capability.
0, enable switch address learning.
50
Mode
Mode
Mode
R/W
R/W
R/W
R/W
R/W
R/W
Pin PMRXD2
strap option. Pull-
down (0): disable
back pressure.
Pull-up(1): enable
back pressure.
Note: PMRXD2
has internal pull-
down.
M9999-091508
Default
Default
Default
1
1
0
0
1