ADAU1961WBCPZ Analog Devices Inc, ADAU1961WBCPZ Datasheet - Page 55

• Manufacturer Part Number: ADAU1961WBCPZ
• Description: IC STEREO AUD CODEC LP 32LFCSP
• Manufacturer: Analog Devices Inc
• Type: Audio Codecr

Specifications of ADAU1961WBCPZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 99 / 101
• Dynamic Range, Adcs / Dacs (db) Typ: 99 / 101
• Voltage - Supply, Analog: 2.97 V ~ 3.63 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN, CSP Exposed Pad
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 2
• No. Of Output Channels: 2
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 101dB
• Sampling Rate: 96kSPS
• No. Of: RoHS Compliant
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

R16: Serial Port Control 1, 16,406 (0x4016)
Bit 7
Table 41. Serial Port Control 1 Register
Bits
[7:5]
4
3
2
[1:0]
Bit Name
BPF[2:0]
ADTDM
DATDM
MSBP
LRDEL[1:0]
Bit 6
BPF[2:0]
Description
Number of bit clock cycles per LRCLK audio frame.
Setting
000
001
010
011
100
101
110
111
ADC serial audio data channel position in TDM mode.
0 = left first (default).
1 = right first.
DAC serial audio data channel position in TDM mode.
0 = left first (default).
1 = right first.
MSB position in the LRCLK frame.
0 = MSB first (default).
1 = LSB first.
Data delay from LRCLK edge (in BCLK units).
Setting
00
01
10
11
Bit 5
Bit 4
ADTDM
Bit Clock Cycles
64 (default)
32
48
128
256
Reserved
Reserved
Reserved
Delay (Bit Clock Cycles)
1 (default)
0
8
16
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Bit 3
DATDM
Bit 2
MSBP
Bit 1
LRDEL[1:0]
ADAU1961
Bit 0