ADAU1961WBCPZ Analog Devices Inc, ADAU1961WBCPZ Datasheet - Page 56

• Manufacturer Part Number: ADAU1961WBCPZ
• Description: IC STEREO AUD CODEC LP 32LFCSP
• Manufacturer: Analog Devices Inc
• Type: Audio Codecr

Specifications of ADAU1961WBCPZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 99 / 101
• Dynamic Range, Adcs / Dacs (db) Typ: 99 / 101
• Voltage - Supply, Analog: 2.97 V ~ 3.63 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN, CSP Exposed Pad
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 2
• No. Of Output Channels: 2
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 101dB
• Sampling Rate: 96kSPS
• No. Of: RoHS Compliant
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADAU1961
R17: Converter Control 0, 16,407 (0x4017)
Bit 7
Reserved
Table 42. Converter Control 0 Register
Bits
[6:5]
4
3
[2:0]
R18: Converter Control 1, 16,408 (0x4018)
Bit 7
Table 43. Converter Control 1 Register
Bits
[1:0]
Bit Name
DAPAIR[1:0]
DAOSR
ADOSR
CONVSR[2:0]
Bit Name
ADPAIR[1:0]
Bit 6
Bit 6
Description
On-chip DAC serial data selection in TDM mode.
Setting
00
01
10
11
DAC oversampling ratio. This bit cannot be set for 64× when CONVSR[2:0] is set to 96 kHz.
0 = 128× (default).
1 = 64×.
ADC oversampling ratio. This bit cannot be set for 64× when CONVSR[2:0] is set to 96 kHz.
0 = 128× (default).
1 = 64×.
Converter sampling rate. The ADCs and DACs operate at the sampling rate set in this register. The converter rate
selected is a ratio of the base sampling rate, f
of the core clock. The serial port mirrors the converter sampling rates set in this register.
Setting
000
001
010
011
100
101
110
111
Description
On-chip ADC serial data selection in TDM mode.
Setting
00
01
10
11
DAPAIR[1:0]
Bit 5
Bit 5
Reserved
Bit 4
DAOSR
Bit 4
Pair
First pair (default)
Second pair
Third pair
Fourth pair
Sampling Rate
f
f
f
f
f
f
f
Reserved
Pair
First pair (default)
Second pair
Third pair
Fourth pair
S
S
S
S
S
S
S
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Bit 3
ADOSR
Bit 3
S
. The base sampling rate is determined by the operating frequency
Bit 2
Bit 2
Base Sampling Rate (f
48 kHz, base (default)
8 kHz
12 kHz
16 kHz
24 kHz
32 kHz
96 kHz
Bit 1
Bit 1
CONVSR[2:0]
S
= 48 kHz)
ADPAIR[1:0]
Bit 0
Bit 0