ADNS-5060 Avago Technologies US Inc., ADNS-5060 Datasheet - Page 15

• Manufacturer Part Number: ADNS-5060
• Description: IC USB OPT MOUSE SENSOR HS 8-DIP
• Manufacturer: Avago Technologies US Inc.

Specifications of ADNS-5060

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SCLK
SDIO
Power-down Mode (PD) and Timing
ADNS-5060 Power-down mode
ADNS-5060 can be placed in a power-down mode by
setting bit 6 in the configuration register via a serial I/O
port write operation. Note that while writing a “1” to bit 6
of the configuration register, all other bits must be written
with their original value in order to keep the current
configuration. After setting the configuration register,
wait at least 32 system clock cycles. To get the chip out
of the power-down mode, clear bit 6 in the configuration
register via a serial I/O port write operation. (CAUTION!
In power-down mode, the SPI timeout (t
SCLK
SDIO
Figure 11: Power-down timing
The address of the configuration register is 1000000 (retail
option). Assume that the original content of the configu-
ration register is 0x00.
Figure 12: Power Down configuration register writing operation
Setting the power down bit simply sets the analog circuitry
into a no current state.
Note: LED_CNTL and SDIO will be tri-stated during power down mode.
15
CLK
I
DD
Operation
Write
1
1
1
Con- g uration Register Address
0
A
6
A
0
5
A
4
0
A
3
0
0
SPTT
D
5
0
) will not
D
4
0
D
3
Con- g uration Register Data (0x40)
D
1
2
D
function. Therefore, no partial SPI command should be
sent. Otherwise, the sensor may go into a hang-up state).
While the sensor is in power-down mode, only the bit 6
data will be written to the configuration register. Writing
the other configuration register values will not have any
effect. For an accurate report after power-up, wait for a
total period of 50ms before the microcontroller is able
to issue any write/read operation to the ADNS-5060. The
sensor register settings, prior to power-down mode, will
remain during power-down mode.
1
0
D
0
0
32 clock cycles min
0
t
PD
0
0
0