ADNS-5060 Avago Technologies US Inc., ADNS-5060 Datasheet - Page 21

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ADNS-5060

Manufacturer Part Number
ADNS-5060
Description
IC USB OPT MOUSE SENSOR HS 8-DIP
Manufacturer
Avago Technologies US Inc.
Datasheet

Specifications of ADNS-5060

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADNS-5060
Manufacturer:
MICRON
Quantity:
60
SCLK
SDIO
SCLK
SDIO
Notes on Power-up and the Serial Port
The sequence in which V
power-up can affect the operation of the serial port. The
diagram below shows what can happen shortly after
Figure 25. Power-up serial port sequence
This diagram shows the V
point the microcontroller starts it’s program, sets the SCLK
and SDIO lines to be outputs, and sets them high. Then,
the microcontroller waits to ensure the ADNS-5060 has
powered up and is ready to communicate. The micro-
processor then tries to read from location 0x41, Status
register, and is expecting a value of 0x0b010XXXXX. If it
receives this value, then it knows the communication to
the ADNS-5060 is operational.
The problem occurs if the ADNS-5060 powers up before
the microprocessor sets the SCLK and SDIO lines to be
outputs and high. The ADNS-5060 sees the raising of the
SCLK as a valid rising edge, and clocks in the state of the
Solution
One way to solve the problem is by waiting for the serial
port timer to time out.
1. Serial Port Timer Timeout
Figure 26. Power up serial port timer sequence
21
V
V
DD
DD
Problem Area
>t
DD
DD
SPTT
, SCLK and SDIO are set during
rising to valid levels, at some
Address = 0x41
Address = 0x41
Data = 0x0b010XXXXX
power-up when the microprocessor tries to read data
from the serial port.
SDIO as the first bit of the address (sets either a read or a
write, depending upon the state).
In the case of a SDIO low, a read operation will start. When
the microprocessor actually begins to send the address,
the ADNS-5060 already has the first bit of an address.
When the seventh bit is sent by the microprocessor, the
ADNS-5060 has a valid address, and drives the SDIO line
high within 250 ns (see detail “A” in Figure 18 and Figure
19). This results in a bus fight for SDIO. Since the address
is wrong, the data sent back would be incorrect.
In the case of a SDIO high, a write operation will start. The
address and data will be out of synchronization, causing
the wrong data written to the wrong address.
Data = 0x0b010XXXXX
Don't Care State

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