ADNS-5060 Avago Technologies US Inc., ADNS-5060 Datasheet - Page 18

• Manufacturer Part Number: ADNS-5060
• Description: IC USB OPT MOUSE SENSOR HS 8-DIP
• Manufacturer: Avago Technologies US Inc.

Specifications of ADNS-5060

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Read Operation
A read operation, means data that is going from the ADNS-
5060 to the microcontroller, is always initiated by the mi-
crocontroller and consists of two bytes. The first byte that
contains the address is written by the microcontroller and
has a “0” as its MSB to indicate data direction. The second
byte contains the data and is driven by the ADNS-5060.
The transfer is synchronized by SCLK. SDIO is changed on
falling edges of SCLK and read on every rising edge of SCLK.
Figure 18. Read operation
Detail “A”
Microcontroller
to ADNS-5060
SDIO handoff
Figure 19. Microcontroller to ADNS-5060 SDIO handoff
Figure 20. ADNS-5060 to microcontroller SDIO handoff
18
Detail “B”
ADNS-5060 to
Microcontroller
SDIO hando-
Cycle #
SCLK
SCLK
SDIO
1
0
SCLK
SCLK
SDIO
SDIO
A
2
6
Released by ADNS-5060
A
SDIO Driven by Micro-Controller
3
A
1
5
4
A
4
D
t
0
HOLD
A
5
3
60ns, min
6
A
2
R/W bit of next address
7
A
160ns, max
250ns, min
1
A
Driven by microcontroller
0
A
0
t
8
Detail "A"
SRAD
0ns, min
9
D
7
The microcontroller must go to a high-Z state after the
last address data bit. The ADNS-5060 will go to the high-Z
state after the last data bit. Another thing to note during a
read operation is that SCLK needs to be delayed after the
last address data bit to ensure that the ADNS-5060 has at
least 100 us to prepare the requested data. This is shown
in the timing diagrams below (See Figures 18 to 20).
10
D
6
11
SDIO Driven by ADNS-5060
D
NOTE: The 250 ns high state of SCLK is the minimum data
hold time of the ADNS-5060. Since the falling edge of SCLK
is actually the start of the next read or write command, the
ADNS-5060 will hold the state of D
the falling edge of SCLK. In both write and read operations,
SCLK is driven by the microcontroller.
5
Hi-Z
12
D
250ns,max
4
13
160ns, min
D
D
3
7
14
D
2
D
15
6
D
250ns,max
1
16
Detail "B"
D
0
0
on the SDIO line until