ispPAC-CLK5304S-01TN48I Lattice, ispPAC-CLK5304S-01TN48I Datasheet - Page 32

• Manufacturer Part Number: ispPAC-CLK5304S-01TN48I
• Description: Clock Drivers & Distribution ISP 0 Delay Unv Fan- Out Buf-Sngl End I
• Manufacturer: Lattice
• Type: Zero Delay Programmable PLL Clock Generatorr

Specifications of ispPAC-CLK5304S-01TN48I

• Max Input Freq: 267 MHz
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
ispClock5300S Family Data Sheet
(f
= 400MHz) to 780ps (f
= 160MHz), which is twice as long as those provided in fine skew mode. When
VCO
VCO
coarse skew mode is selected, an additional divide-by-2 stage is effectively inserted between the VCO and the V-
divider bank, as shown in Figure 26. When assigning divider settings in coarse skew mode, one must account for
this additional divide-by-two so that the VCO still operates within its specified range (160-400MHz).
Figure 26. Additional Factor-of-2 Division in Coarse Mode
Fine
Mode
VCO
V-dividers
Fout
Coarse
Mode
÷2
When one moves from fine skew mode to coarse skew mode with a given divider configuration, the VCO frequency
will attempt to double to compensate for the additional divide-by-2 stage. Because the f
range is not increased,
VCO
however, one must modify the feedback path V-divider settings to bring f
back into its specified operating range
VCO
(160MHz to 400MHz). This can be accomplished by dividing all V-divider settings by two. All output frequencies will
remain unchanged from what they were in fine mode.
Output Skew Matching and Accuracy
Understanding the various factors which relate to output skew is essential for realizing optimal skew performance in
the ispClock5300S family of devices.
In the case where two outputs are identically configured, and driving identical loads, the maximum skew is defined
by t
which is specified as a maximum of 100ps. In Figure 27 the Bank1A and BANK2A outputs show the skew
SKEW,
error between two matched outputs.
Figure 27. Skew Matching Error Sources
1ns +/- (t
) +/- (t
)
SKEW
SKERR
+/- t
SKEW
BANK1A
(skew setting = 0)
BANK2A
(skew setting=0)
BANK3A
(skew setting = 1ns)
One can also program a user-defined skew between two outputs using the skew control units. Because the pro-
grammable skew is derived from the VCO frequency, as described in the previous section, the absolute skew is
very accurate. The typical error for any non-zero skew setting is given by the t
specification. For example, if
SKERR
one is in fine skew mode with a VCO frequency of 250MHz, and selects a skew of 4TU, the realized skew will be
1ns, which will typically be accurate to within +/-30 ps. An example of error vs. skew setting can be found in the
chart ‘Typical Skew Error vs. Setting’ in the typical performance characteristics section. Note that this parameter
adds to output-to-output skew error only if the two outputs have different skew settings. The Bank1A and Bank3A
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