LAN9312-NU SMSC, LAN9312-NU Datasheet - Page 323
LAN9312-NU
Manufacturer Part Number
LAN9312-NU
Description
Ethernet ICs Hi Per 2 Port 10/100 Ethernet Switch
Manufacturer
SMSC
Type
Two Port Managed Ethernet Switchr
Datasheet
1.LAN9312-NZW.pdf
(458 pages)
Specifications of LAN9312-NU
Ethernet Connection Type
10 Base-T, 100 Base-TX
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Product
Ethernet Switches
Number Of Transceivers
1
Standard Supported
802.3, 802.3u
Data Rate
10 Mbps, 100 Mbps
Supply Voltage (max)
3.3 V
Supply Voltage (min)
0 V
Supply Current (max)
185 mA, 295 mA
Maximum Operating Temperature
+ 70 C
Package / Case
TQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LAN9312-NU
Manufacturer:
Microchip Technology
Quantity:
10 000
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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
14.5.2.2
BITS
31:8
7
6
5
4
3
2
1
0
RESERVED
RESERVED
Note:
RESERVED
Enable Receive Own Transmit
When set, the switch port will receive its own transmission if it is looped back
from the PHY. Normally, this function is only used in Half Duplex PHY
loopback.
RESERVED
Jumbo2K
When set, the maximum packet size accepted is 2048 bytes. Statistics
boundaries are also adjusted.
RESERVED
Reject MAC Types
When set, MAC control frames (packets with a type field of 8808h) are
filtered. When cleared, MAC Control frames, other than MAC Control Pause
frames, are sent to the forwarding process. MAC Control Pause frames are
always consumed by the switch.
RX Enable
When set, the receive port is enabled. When cleared, the receive port is
disabled.
Port x MAC Receive Configuration Register (MAC_RX_CFG_x)
This read/write register configures the packet type passing parameters of the port.
This bit must always be written as 0.
Register #:
Port0: 0401h
Port1: 0801h
Port2: 0C01h
DESCRIPTION
DATASHEET
323
Size:
32 bits
TYPE
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
Revision 1.7 (06-29-10)
DEFAULT
0b
0b
0b
1b
1b
-
-
-
-
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