LAN91C96TQFP SMSC, LAN91C96TQFP Datasheet - Page 50

• Manufacturer Part Number: LAN91C96TQFP
• Description: Ethernet ICs Non-PCI 10 Mbps Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN91C96TQFP

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 95 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.0 (10-24-08)
A15
0
INT SEL1-0 - In LOCAL BUS mode, used to select one out of four interrupt pins. The three
unused interrupts are tristated.
INT SEL1
I/O SPACE - BANK1
For LOCAL BUS mode only, this register holds the I/O address decode option chosen for the I/O and ROM
space. It is part of the EEPROM saved setup, and is not usually modified during run-time.
A15 - A13 and A9 - A5 - These bits are compared in LOCAL BUS mode against the I/O address on the
bus to determine the IOBASE for LAN91C96 registers. The 64k I/O space is fully decoded by the
LAN91C96 down to a 16 location space, therefore the unspecified address lines A4, A10, A11 and A12
must be all zeros.
ROM SIZE - Determines the ROM decode area in LOCAL BUS mode memory space as follows:
00 = ROM disable
01 = 16k: RA14-18 define ROM select.
10 = 32k: RA15-18 define ROM select.
11 = 64k: RA16-18 define ROM select.
RA18-RA14 - These bits are compared in LOCAL BUS mode against the memory address on the bus to
determine if the ROM is being accessed, as a function of the ROM SIZE. ROM accesses are read only
memory accesses defined by MEMRD* going low.
For a full decode of the address space unspecified upper address lines have to be: A19 = "1", A20-A23
lines are not directly decoded, however LOCAL BUS systems will only activate SMEMRD* only when A20-
A23=0.
All bits in this register are loaded from the serial EEPROM in LOCAL BUS Mode only. In PCMCIA mode,
the I/O base is set to the default value (as in LOCAL BUS mode) as defined below.
The I/O base decode defaults to 300h (namely, the high byte defaults to 18h). ROM SIZE defaults to 01.
ROM decode defaults to CC000 (namely the low byte defaults to 67h).
Below chart shows the decoding of I/O Base Address 300h:
A14
0
0
1
1
A15
0
OFFSET
0
0
ROM SIZE
2
A13
0
A14
A12
0
1
INT SEL0
0
0
1
0
1
BASE ADDRESS REGISTER
A11
0
A13
0
1
A10
RA18
0
NAME
DATASHEET
INTERRUPT PIN USED
INTR0
INTR1
INTR2
INTR3
A9
1
A9
1
0
RA17
A8
1
Page 50
A7
Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
0
A8
1
0
RA16
A6
0
READ/WRITE
TYPE
A5
0
A7
0
1
RA15
A4
0
A3
A6
0
0
1
RA14
SYMBOL
BAR
A2
0
SMSC LAN91C96 5v&3v
A5
0
1
A1
0
Datasheet
A0
0