LAN91C96TQFP SMSC, LAN91C96TQFP Datasheet - Page 57

• Manufacturer Part Number: LAN91C96TQFP
• Description: Ethernet ICs Non-PCI 10 Mbps Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN91C96TQFP

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 95 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Datasheet
SMSC LAN91C96 5v&3v
I/O SPACE - BANK2
RCV
POINTER REGISTER - The value of this register determines the address to be accessed within the
transmit or receive areas. It will auto-increment on accesses to the data register when AUTO INCR. is set.
The increment is by one for every byte access, and by two for every word access. When RCV is set the
address refers to the receive area and uses the output of RX FIFO as the packet number, when RCV is
clear the address refers to the transmit area and uses the packet number at the Packet Number Register.
READ bit - Determines the type of access to follow. If the READ bit is high the operation intended is a
read. If the READ bit is low the operation is a write. Loading a new pointer value, with the READ bit high,
generates a pre-fetch into the Data Register for read purposes.
Read-back of the pointer will indicate the value of the address last accessed by the CPU (rather than the
last pre-fetched). This allows any interrupt routine that uses the pointer, to save it and restore it without
affecting the process being interrupted.
The Pointer Register should not be loaded until 400ns after the last write operation to the Data Register to
ensure that the Data Register FIFO is empty. On reads, if IOCHRDY is not connected to the host, the Data
Register should not be read before 400ns after the pointer was loaded to allow the Data Register FIFO to
fill.
If the pointer is loaded using 8 bit writes, the low byte should be loaded first and the high byte last.
Reserved – Must be 0.
If AUTO INCR. is not set, the pointer must be loaded with an even value.
I/O SPACE - BANK2
DATA REGISTER - Used to read or write the data buffer byte/word presently addressed by the pointer
register.
OFFSET
OFFSET
0
0
8 & A
6
AUTO
INCR.
0
0
READ
POINTER REGISTER
0
0
DATA REGISTER
DATASHEET
NAME
NAME
Reserved
POINTER LOW
0
0
DATA HIGH
DATA LOW
Page 57
Reserved
0
0
READ/WRITE
READ/WRITE
0
0
TYPE
TYPE
POINTER HIGH
0
0
SYMBOL
SYMBOL
DATA
PTR
Revision 1.0 (10-24-08)
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