LAN91C96TQFP SMSC, LAN91C96TQFP Datasheet - Page 83
![Ethernet ICs Non-PCI 10 Mbps Ethernet MAC](/photos/27/13/271359/lan9116_sml.jpg)
LAN91C96TQFP
Manufacturer Part Number
LAN91C96TQFP
Description
Ethernet ICs Non-PCI 10 Mbps Ethernet MAC
Manufacturer
SMSC
Type
Single Chip MAC and PHY Controllerr
Datasheet
1.LAN91C96-MU.pdf
(125 pages)
Specifications of LAN91C96TQFP
Ethernet Connection Type
10 Base-T, 100 Base-TX
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Product
Ethernet Controllers
Number Of Transceivers
1
Standard Supported
802.3, 802.3u
Data Rate
10 Mbps, 100 Mbps
Supply Voltage (max)
5 V
Supply Voltage (min)
0 V
Supply Current (max)
95 mA
Maximum Operating Temperature
+ 70 C
Package / Case
TQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Datasheet
SMSC LAN91C96 5v&3v
DMA block when the CSMA/CD block is ready to proceed on to the next transmission. By reading the TX
EMPTY INT bit the CPU can determine if this FIFO is empty.
The transmit completion FIFO stores the packet numbers that were already transmitted but not yet
acknowledged by the CPU. The CPU can read the next packet number in this FIFO from the FIFO Ports
Register. The CPU can remove a packet number from this FIFO by issuing a TX INT acknowledge. The
CPU can determine if this FIFO is empty by reading the TX INT bit or the FIFO Ports Register.
The receive packet FIFO stores the packet numbers already received into memory, in the order they were
received. The FIFO is advanced (written) by the DMA block upon reception of a complete valid packet into
memory. The number is determined the moment the DMA block first requests memory from the MMU for
that packet. The first receive packet number in the FIFO can be read via the FIFO Ports Register, and the
data associated with it can be accessed through the receive area. The packet number can be removed
from the FIFO with or without an automatic release of its associated memory.
The FIFO is read out upon CPU command (remove packet from top of RX FIFO, or remove and release
command) after processing the receive packet in the receive area.
The width of each FIFO is 5 bits per packet number. The depth of each FIFO equals the number of
packets the LAN91C96 can handle (18).
The guideline is software transparency; the software driver should not be aware of different devices or
FIFO depths. If the MMU memory allocation succeeded, there will be room in the transmit FIFO for
enqueuing the packet. Conversely if there is free memory for receive, there should be room in the receive
FIFO for storing the packet number.
Note that the CPU can enqueue a transmit command with a packet number that does not follow the
sequence in which the MMU assigned packet numbers. For example, when a transmission failed and it is
retried in software, or when a receive packet is modified and sent back to the network.
DATASHEET
Page 83
Revision 1.0 (10-24-08)
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