S19233PBIFB AMCC, S19233PBIFB Datasheet - Page 11

• Manufacturer Part Number: S19233PBIFB
• Description: Ethernet/Fibre Channel 49-Pin BGA
• Manufacturer: AMCC

Specifications of S19233PBIFB

• Package: 49BGA
• Maximum Data Rate: 11.32 Gbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 380 mA
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.65|3.03 V
• Maximum Operating Supply Voltage: 1.95|3.56 V

S19233 – 10 G Ethernet/Fibre Channel/SONET/SDH
Dual CDR
Transmit Output Polarity Invert
The output data polarity swap is implemented for the
ease of design. This adds routing flexibility for either
t o p o r b o t t o m P C B p l a c e m e n t o f I C o r o p t i c s
compatibility.
When the TX_POLINV is set high through the I
interface, the polarity of the transmitter output is
inverted.
Transmit Output Squelch
The output data squelch functions are controlled
through the I
polarity of the receive squelch data and TX_SQ_EN is
the control bit used to enable or disable the squelch
feature. The TX_SQ_CNTL bit is a transmit squelch
control bit. See Table 4 for details.
Table 4. Transmit Squelch Control
AMCC Confidential and Proprietary
TX_SQ_
EN
0
1
1
TX_SQ_CNTL
2
C interface. TX_SQ_POL determines the
X
0
1
Disable Squelch
Squelch TX data
Default mode. TXLOCK signal
controls the squelch.
Function
2
C
TRANSMIT ELECTRICAL SIDE – CON-
TROL DESCRIPTION
Transmit Serial Data In (TXDATIP/N) – External Pin
The Transmit Data In (TXDATIP/N) pins are differential
Current Mode Logic (CML) inputs. They receive inputs
via a PWB trace which can be up to 10 inches in
length. The TXDATIP/N is internally terminated with
two 50 Ω resistors in series. The two 50 Ω resistors
are center-tapped with a 850 pF capacitor for use in
single-ended applications.
The TXDATIP/N inputs must be AC coupled. These
pins are internally biased and terminated 100
to-line.
Transmit Loop Filter (TXCAP1, TXCAP2) – External
Pin
The CDR external loop filter capacitor and resistors
are connected to the TXCAP1 and TXCAP2 pins.
These devices should be surrounded by a ground
shield. Component values should be as stated in Table
19, Transmit and Receive External Loop Filter
Components.
Transmit Lock (TXLOCk) – External Pin
TXLOCK goes active after the transmit PLL has locked
on the incoming data stream after initially locking onto
the clock provided on the REFCLK pins. TXLOCK is
an asynchronous output. The Transmit Lock status is
also available as TXLOCK read only register bit.
Transmit Lock-to-Reference (LCKREFTXB) – I
Register
Active low. Lock-to-Reference (LCKREFTXB) will
force the PLL to lock to the local Reference Clock
(REFCLK) when active. This bit should be set to inac-
tive which is default, for normal operation. This input is
only accessible through the I
Transmit Squelch Serial Output (TX_SQ_EN) – I
Register
Squelch Serial Output data enable (TX_SQ_EN),
when asserted high, will enable the squelch function in
the transmitter.
Revision 5.00 – March 16, 2007
2
C bus register.
Data Sheet
Ω
2
line-
C
2
C
11