S19233PBIFB AMCC, S19233PBIFB Datasheet - Page 6

• Manufacturer Part Number: S19233PBIFB
• Description: Ethernet/Fibre Channel 49-Pin BGA
• Manufacturer: AMCC

Specifications of S19233PBIFB

• Package: 49BGA
• Maximum Data Rate: 11.32 Gbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 380 mA
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.65|3.03 V
• Maximum Operating Supply Voltage: 1.95|3.56 V

S19233 – 10 G Ethernet/Fibre Channel/SONET/SDH
Dual CDR
S19233 OVERVIEW
The S19233 can be used to implement the front end of
SONET/SDH/FEC/10GbE/FC/G.709 equipment which
consists primarily of the serial transmit interface and
the serial receive interface. The system timing circuitry
consists of a high-speed phase detector, clock and
data recovery unit and equalization circuitry. The
device utilizes on-chip clock recovery PLL compo-
nents that allow the use of a slower external clock
reference, 155.52 MHz (or equivalent FEC/10GbE/
10 Gbps FC rate), in support of existing system clock-
ing schemes.
The EDC function is embedded in the optical receive
side. It provides control to compensate chromatic dis-
persion in different fiber links. On the transmitter side,
an equalizer is integrated in the receive front end to
reshape the data after transmission over FR-4. This
enables low bit error rate and transmission over longer
trace length.
The low-jitter, 1-bit, CML interfaces guarantee compli-
ance with the bit-error rate requirements of the
Telcordia and ITU-T standards. The 10 Gbps serial
electrical interface specifications are compliant with
the XFI as specified in the XFP MSA module specifica-
tion. The high speed serial input and output can be
connected to the AMCC SerDes (S19235 or S19237)
across 600 mm (24”) of improved FR-4 material or
across 400 mm of standard FR-4 with one connector.
Table 2 shows the suggested interface device(s) for
the S19233.
Table 1. Standard Compliance List
Note: Standards compliance only relates to applicable sections pertaining to
6
XFP - 10 Gigabit Small Form Factor
Pluggable Module
T1.105.03 - 2002 SONET Jitter Toler-
ance specification
GR-253-CORE
GR-253-ILR- Sonet Jitter Specifications
G.825 SDH Jitter Tolerance specification
G.783 Characteristics of synchronous
digital hierarchy (SDH) equipment func-
tional blocks
IEEE 802.3ae
X3.T11 FC-PH-3 10 G
ESD - JEDEC standard: JESD22-A114-B
this product type.
Standard
Revision
Issue 3A
Rev 0
Rev B
4.0
3.0
-
-
-
-
Date
4/13/04
08/2002
09/2000
10/2000
03/2000
02/2004
8/30/2002
5/2003
6/2000
Transmitter Side Operations
Receiver Side Operations
Common Operations
Table 2. AMCC Suggested Interface Devices
POWER UP SEQUENCE
This Power Up Sequence provides details for the
required reset sequence to initialize the S19233 fol-
lowing power on or system reset.
The initialization will complete in 13 clock cycles fol-
lowing the falling edge of the PD signal. The PD signal
must remain low for normal operation.
1. 1-bit serial data input
2. Equalization to compensate for FR-4
3. Threshold and Offset cancellation adjust
4. Clock and Data recovery
5. Data retime
6. Serial data output
1. Serial input with AGC (Equalization)
2. 10 mV
3. Loss of signal detection
4. Clock and Data recovery
5. Serial data output
1. Optical and Electrical Loopbacks
2. Power Down CDR
AMCC
AMCC
3. Apply the reference clock to pin REFCLKP/N
4. Set pin PD high for at least two clock cycles then
adjust
set low to initiate initialization and for normal
operation.
S19235
S19237
pp
Differential Sensitivity with threshold
SFI4 Phase 1
SONET/SDH STS-192/10 Gig Ether-
net CMOS Transceiver with ISI Com-
pensation
SFI4 Phase 1
SONET/SDH STS-192/10 Gig Ether-
net CMOS Transceiver with ISI Com-
pensation
Revision 5.00 – March 16, 2007
AMCC Confidential and Proprietary
Data Sheet