S19233PBIFB AMCC, S19233PBIFB Datasheet - Page 9

• Manufacturer Part Number: S19233PBIFB
• Description: Ethernet/Fibre Channel 49-Pin BGA
• Manufacturer: AMCC

Specifications of S19233PBIFB

• Package: 49BGA
• Maximum Data Rate: 11.32 Gbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 380 mA
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.65|3.03 V
• Maximum Operating Supply Voltage: 1.95|3.56 V

S19233 – 10 G Ethernet/Fibre Channel/SONET/SDH
Dual CDR
Receiver Output Polarity Invert
The output data polarity swap is implemented for the
ease of design. This adds routing flexibility for either
t o p o r b o t t o m P C B p l a c e m e n t o f I C o r o p t i c s
compatibility.
When the RX_POLINV is set high through the I
interface, the polarity of the receiver output is inverted.
Receiver Output Squelch
The output data squelch functions are controlled
through the I2C BUS
mines the polarity of the receive squelch data and
RX_SQ_EN is the control bit used to enable or disable
the squelch feature. The RX_SQ_CNTL bit is a
receiver squelch control bit. See Table 3 for details.
Table 3. Receive Squelch Control
AMCC Confidential and Proprietary
RX_SQ
_EN
1
1
1
1
1
0
RX_SQ
_CNTL
X
0
1
1
1
1
RX_SQ[1:0]
®
interface. RX_SQ_POL deter-
XX
XX
00
01
10
11
Squelch RX data
LOS_SD (LOS) out-
put controls the
squelch
RXLOCK signal con-
trols the squelch.
The LOS condition
will also trigger
RXLOCK.
LOS_SD (SD) input
control the squelch
(1) RX squelch func-
tion is controlled by
LOS or RXLOCK
(Default: LOS_SDC
is active high)
(2) RX squelch func-
tion is controlled by
SD or RXLOCK if
LOS_SD is low
Disable squelch fea-
ture for RX
Function
2
C
RECEIVE OPTICAL SIDE – CONTROL
DESCRIPTION
Receive Serial Data In (RXDATINP/N) – External
Pin
The Receive Data In (RXDATIP/N) pins are differential
Current Mode Logic (CML) inputs. They receive inputs
from an optics module or other upstream logic device.
The RXDATIP/N is internally terminated with two 50 Ω
resistors in series. The two 50 Ω resistors are center-
tapped with a 25 pF capacitor for use in single-ended
applications.
The RXDATIP/N inputs must be AC coupled. These
pins are internally biased and terminated 100
to-line.
RXDATIP/N Internal Center-Tapped Termination
(RXCTAP) – External Pin
The RXDATIP/N is internally terminated with two 50 Ω
resistors in series. The two 50 Ω resistors are center-
tapped with a 25 pF capacitor. The input to the capaci-
tor can be directly accessed through the RXCTAP pin.
This input should be connected to a broadband 850 pF
capacitor to ground when used in single-ended appli-
cations. This termination scheme enables the S19233
to be driven in the single-ended mode and offers better
common-mode noise rejection. This input should be
left floating if RXDATIP/N is driven differentially.
Receive Loop Filter (RXCAP1, RXCAP2) – External
Pin
The CDR external loop filter capacitor and resistors
are connected to the RXCAP1 and RXCAP2 pins.
These devices should be surrounded by a ground
shield. Component values should be as stated in Table
19, Transmit and Receive External Loop Filter
Components.
Receive Lock (RXLOCK) – External Pin
RXLOCK goes active after the receive PLL has locked
on the incoming data stream after initially locking onto
the clock provided on the REFCLK pins. RXLOCK is
an asynchronous output. The Receive Lock status is
also available as RXLOCK register read only bit.
Receive Loss of Signal/Signal Detect (LOS_SD) –
External Shared Pin
This is a dual purpose pin. This pin is configured as a
Loss of Signal (LOS) pin or can be changed to a Sig-
nal Detect (SD) pin through the I
LOS_SD bit
or active low by setting RX_LOS_POL bit to 1 or 0
respectively. The LOS threshold and hysteresis are
adjustable via the I
. The LOS can be programmed active high
2
C control registers. Upon receiving
Revision 5.00 – March 16, 2007
2
C interface using the
Data Sheet
Ω
line-
9