MT48H8M32LFB5-75 IT:H Micron Technology Inc, MT48H8M32LFB5-75 IT:H Datasheet - Page 53

• Manufacturer Part Number: MT48H8M32LFB5-75 IT:H
• Description: DRAM Chip Mobile SDRAM 256M-Bit 8Mx32 1.8V 90-Pin VFBGA Tray
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M32LFB5-75 IT:H

• Density: 256 Mb
• Maximum Clock Rate: 133 MHz
• Package: 90VFBGA
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 1.8 V
• Maximum Random Access Time: 8|6 ns
• Operating Temperature: -40 to 85 °C
• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Package / Case: 90-VFBGA
• Organization: 8Mx32
• Address Bus: 14b
• Access Time (max): 8/6ns
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 100mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PDF:09005aef8219eeeb/Source: 09005aef8219eedd
256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN
22. V
23. The clock frequency can only be changed during clock stop, power-down, or while in
24. Auto precharge mode only. The precharge timing budget (
25. Parameter guaranteed by design.
26. CKE is HIGH during refresh command period
27. The I
28. Values for I
29. Deep power-down current is a nominal value at 25°C. This parameter is not tested.
30. Test conditions include 500ms delay prior to measurement.
31. Auto precharge mode only. The precharge timing budget (
not be greater than one third of the cycle rate. V
width ≤ 3ns.
a self-refresh mode.
after the first clock delay, after the last WRITE is executed. May not exceed limit set for
precharge mode.The clock frequency can only be changed during
only. Values for I
and 7ns for -8 after the first clock delay, after the last WRITE is executed. For auto pre-
charge mode, at least one clock cycle is required during
IH
overshoot: V
DD6
limit is actually a nominal value and does not result in a fail value.
DD7
for 70°C, 45°C, 15°C, and I
DD7
IH,max
4-bank, 2-bank, and 1-bank for 85°C are 100% tested.
= V
DDQ
53
+ 2V for a pulse width ≤ 3ns, and the pulse width can-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD7
256Mb: x16, x32 Mobile SDRAM
t
RFC (MIN), else CKE is LOW.
IL
1/2-bank and 1/4-bank are sampled
undershoot: V
t
WR.
t
RP) begins at 7.5ns for -75
©2006 Micron Technology, Inc. All rights reserved.
t
RP) begins at 7ns for -8
IL,min
= –2V for a pulse
Notes