MT48LC32M8A2TG-75:D Micron Technology Inc, MT48LC32M8A2TG-75:D Datasheet - Page 28
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MT48LC32M8A2TG-75:D
Manufacturer Part Number
MT48LC32M8A2TG-75:D
Description
DRAM Chip SDRAM 256M-Bit 32Mx8 3.3V 54-Pin TSOP-II Tray
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC32M8A2TG-75D.pdf
(87 pages)
Specifications of MT48LC32M8A2TG-75:D
Density
256 Mb
Maximum Clock Rate
133 MHz
Package
54TSOP-II
Address Bus Width
15 Bit
Operating Supply Voltage
3.3 V
Maximum Random Access Time
6|5.4 ns
Operating Temperature
0 to 70 °C
Organization
32Mx8
Address Bus
15b
Access Time (max)
6/5.4ns
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
135mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Not Compliant
Table 15: AC Functional Characteristics (-7E, -75)
Notes 1–5 and note 7 apply to all parameters and conditions
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Parameter
Last data-in to burst STOP command
READ/WRITE command to READ/WRITE command
Last data-in to new READ/WRITE command
CKE to clock disable or power-down entry mode
Data-in to ACTIVE command
Data-in to PRECHARGE command
DQM to input data delay
DQM to data mask during WRITEs
DQM to data High-Z during READs
WRITE command to input data delay
LOAD MODE REGISTER command to ACTIVE or REFRESH command
CKE to clock enable or power-down exit setup mode
Last data-in to PRECHARGE command
Data-out High-Z from PRECHARGE command
Notes:
10. Timing is specified by
1. The minimum specifications are used only to indicate cycle time at which proper opera-
2. An initial pause of 100μs is required after power-up, followed by two AUTO REFRESH
3. AC characteristics assume
4. In addition to meeting the transition rate specification, the clock and CKE must transit
5. Outputs measured at 1.5V with equivalent load:
6.
7. AC operating and I
8. Timing is specified by
9. Timing is specified by
tion over the full temperature range (0˚C ≤ T
T
ensured.
commands, before proper device operation is ensured. (V
up simultaneously. V
command wake-ups should be repeated any time the
ded.
between V
t
reference to V
reference level of 1.5V. If the input transition time is longer than 1ns, then the timing is
measured from V
always be 1.5V referenced to crossover. Refer to Micron technical note TN-48-09.
cycle rate.
Q
HZ defines the time at which the output achieves the open circuit condition; it is not a
A
≤ +85˚C industrial temperature, and -40˚C ≤ T
IH
and V
Electrical Specifications – AC Operating Conditions
OH
50pF
or V
IL,max
IL
DD
SS
(or between V
OL
test conditions have V
t
t
t
CKS. Clock(s) specified as a reference only at minimum cycle rate.
WR plus
WR.
and V
and V
. The last valid data element will meet
CL = 3
CL = 2
28
t
T = 1ns.
IH,min
SSQ
t
RP. Clock(s) specified as a reference only at minimum
must be at same potential.) The two AUTO REFRESH
and no longer from the 1.5V midpoint. CLK should
IL
Micron Technology, Inc. reserves the right to change products or specifications without notice.
and V
Symbol
t
t
ROH(3)
ROH(2)
t
t
t
t
t
CKED
t
t
t
t
t
DQM
DWD
t
t
t
DQD
MRD
DQZ
CCD
DAL
BDL
CDL
PED
RDL
DPL
IH
IL
) in a monotonic manner.
A
= 0V and V
≤ +70˚C commercial temperature, -40˚C ≤
A
256Mb: x4, x8, x16 SDRAM
≤ +105˚C automotive temperature) is
-7E
1
1
1
1
4
2
0
0
2
0
2
1
2
3
2
t
REF refresh requirement is excee-
IH
DD
= 3.0V using a measurement
-75
and V
© 1999 Micron Technology, Inc. All rights reserved.
1
1
1
1
5
2
0
0
2
0
2
1
2
3
2
t
OH before going High-Z.
DDQ
Unit
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
must be powered
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
Notes
10, 13
10, 13
9, 13
11
11
11
11
11
11
11
17
11
11
8
8