MT48LC32M8A2TG-75:D Micron Technology Inc, MT48LC32M8A2TG-75:D Datasheet - Page 44
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MT48LC32M8A2TG-75:D
Manufacturer Part Number
MT48LC32M8A2TG-75:D
Description
DRAM Chip SDRAM 256M-Bit 32Mx8 3.3V 54-Pin TSOP-II Tray
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC32M8A2TG-75D.pdf
(87 pages)
Specifications of MT48LC32M8A2TG-75:D
Density
256 Mb
Maximum Clock Rate
133 MHz
Package
54TSOP-II
Address Bus Width
15 Bit
Operating Supply Voltage
3.3 V
Maximum Random Access Time
6|5.4 ns
Operating Temperature
0 to 70 °C
Organization
32Mx8
Address Bus
15b
Access Time (max)
6/5.4ns
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
135mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Not Compliant
Figure 17: Initialize and Load Mode Register
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
DQML, DQMU
COMMAND
BA0, BA1
A[12:11]
A[9:0],
DQM/
CKE
A10
DQ
CK
T = 100µs
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Power-up:
V
CLK stable
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MIN
DD
and
t CKS
t CMS
T0
NOP
Notes:
t CKH
High-Z
t CMH
SINGLE BANK
ALL BANKS
t CK
PRECHARGE
1. The mode register may be loaded prior to the AUTO REFRESH cycles if desired.
2. If CS is HIGH at clock HIGH time, all commands applied are NOP.
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after command is issued.
5. A12 should be a LOW at
BANKS
T1
ALL
t RP
Precharge
all banks
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Tn + 1
REFRESH
AUTO
t CH
AUTO REFRESH
t RFC
NOP
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NOP
t
P + 1.
44
t CL
To + 1
REFRESH
AUTO
AUTO REFRESH
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t RFC
NOP
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NOP
256Mb: x4, x8, x16 SDRAM
t AS
t AS
LOAD MODE
Tp + 1
REGISTER
CODE
CODE
t AH
t AH
Program Mode Register
5
© 1999 Micron Technology, Inc. All rights reserved.
t MRD
Tp + 2
NOP
Initialization
1, 3, 4
Tp + 3
ACTIVE
BANK
ROW
ROW
DON’T CARE
UNDEFINED