MT48LC32M8A2TG-75:D Micron Technology Inc, MT48LC32M8A2TG-75:D Datasheet - Page 72
![no-image](/images/manufacturer_photos/0/4/441/micron_technology_inc_sml.jpg)
MT48LC32M8A2TG-75:D
Manufacturer Part Number
MT48LC32M8A2TG-75:D
Description
DRAM Chip SDRAM 256M-Bit 32Mx8 3.3V 54-Pin TSOP-II Tray
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC32M8A2TG-75D.pdf
(87 pages)
Specifications of MT48LC32M8A2TG-75:D
Density
256 Mb
Maximum Clock Rate
133 MHz
Package
54TSOP-II
Address Bus Width
15 Bit
Operating Supply Voltage
3.3 V
Maximum Random Access Time
6|5.4 ns
Operating Temperature
0 to 70 °C
Organization
32Mx8
Address Bus
15b
Access Time (max)
6/5.4ns
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
135mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Not Compliant
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- Download datasheet (4Mb)
Figure 42: READ Without Auto Precharge
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Command
BA0, BA1
Address
DQM
CKE
CLK
A10
DQ
t CMS
t CKS
t AS
t AS
t AS
ACTIVE
T0
Bank
Row
Row
t CMH
t AH
t AH
t AH
t CKH
t RCD
t RAS
t RC
t CK
Note:
T1
NOP
1. For this example, BL = 4, CL = 2, and the READ burst is followed by a manual PRECHARGE.
Disable auto precharge
t CL
t CMS
Column m
T2
Bank
READ
t CMH
t CH
CL = 2
T3
NOP
t LZ
t AC
72
T4
NOP
D
OUT
t OH
t AC
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T5
D
NOP
OUT
t OH
t AC
PRECHARGE
Single bank
256Mb: x4, x8, x16 SDRAM
All banks
Bank(s)
T6
D
OUT
t OH
t RP
PRECHARGE Operation
t AC
© 1999 Micron Technology, Inc. All rights reserved.
T7
NOP
D
OUT
t OH
t HZ
Don’t Care
T8
ACTIVE
Row
Bank
Row
Undefined
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